I am trying to add some functionalities to the existing FPGA in USRP.
I went through the mailing list and figured out that the current
Verilog/VHDL code implementation occupies 90% of FPGA’s resources.
there were some mails that pointed that reducing some reveiver
functionalities could free some FPGA resources.
Any help as to how I can proceed with this i.e. reducing receiver
functionality and freeing up FPGA resources? Also if I should try
implementing some easy additonal functionalities in the FPGA,(so as to
damage the USRP board) then which one should I go ahead with?
Are there any C++ blocks that I can try implementing in VHDL/Verilog
FPGA and improve performance?
I would be grateful if some of you could help me / point in the right
directions with the above questions.