Hardware sampling rates


Would it be possible (now)/( or in the future) to be able to change the
sampling rate of the DAC in the USRP2 using an external clock?
I am working on stuff that is pushing what is possible in software
and not having to add extra overhead simply to do up/down
interpolation to get to something that divides into 100M
would be really useful. I have tried the fractional interpolator and it
just sucks too many CPU cycles.

  • Charles

On Mon, Mar 22, 2010 at 01:49, Charles B. [email protected]

I have tried the fractional interpolator and it just sucks too many CPU cycles.

There is one more thing you can try–use the polyphase resampler.
This is a new block by Tom R. based on the Harris book. It
hasn’t gotten a lot of use yet, but it is working so far and is very

gr.pfb_arb_resampler_ccf(resample_rate, taps, size)

‘resample_rate’ is your desired interpolation rate
‘taps’ is the vector of FIR taps to use as the interpolation filter
‘size’ is the number of phases to use in resampler (default=32)

You can use gr.firdes.* to design a filter to create ‘taps’; but the
sample rates to use require special calculation. See:


…for an example using both the polyphase integral interpolator and
the polyphase arbitrary resampler.

In your case, if I recall correctly, your final output filter is a
root-raised-cosine filter. So you’d use the arbitrary resampler to
upsample to your final output sample rate, and use the RRC tap
generator to create the taps for it.


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