GRAS build error on armv7

Rafa_F · July 26, 2013, 1:58pm

We’ve been successful in building dependencies for gnuradio on armv7
platform, however while building GRAS, we got this error:

Scanning dependencies of target gras
[ 13%] Building CXX object
lib/CMakeFiles/gras.dir/__/Theron/Theron/Receiver.cpp.o
[ 13%] Generating GrExtras_Ops.pyc
[ 13%] Generating GrExtras_Ops.pyo
make[2]: warning: Clock skew detected. Your build may be incomplete.
[ 13%] Built target pygen_python_grextras_da046
[ 13%] Swig source
/tmp/ccONtg2w.s: Assembler messages:
/tmp/ccONtg2w.s:3234: Error: bad instruction pause' /tmp/ccONtg2w.s:3243: Error: bad instructionpause’
/tmp/ccONtg2w.s:3266: Error: bad instruction pause' /tmp/ccONtg2w.s:3275: Error: bad instructionpause’
/tmp/ccONtg2w.s:3406: Error: bad instruction pause' /tmp/ccONtg2w.s:3415: Error: bad instructionpause’
/tmp/ccONtg2w.s:4479: Error: bad instruction pause' /tmp/ccONtg2w.s:4488: Error: bad instructionpause’
/tmp/ccONtg2w.s:4511: Error: bad instruction pause' /tmp/ccONtg2w.s:4520: Error: bad instructionpause’
/tmp/ccONtg2w.s:4540: Error: bad instruction pause' /tmp/ccONtg2w.s:4549: Error: bad instructionpause’
/tmp/ccONtg2w.s:4677: Error: bad instruction pause' /tmp/ccONtg2w.s:4686: Error: bad instructionpause’
/tmp/ccONtg2w.s:4735: Error: bad instruction pause' /tmp/ccONtg2w.s:4744: Error: bad instructionpause’
/tmp/ccONtg2w.s:4816: Error: bad instruction pause' /tmp/ccONtg2w.s:4825: Error: bad instructionpause’
make[2]: Warning: File `/usr/include/python2.7/Python.h’ has
modification
time 4.1e+08 s in the future
[ 13%] Building CXX object
PMC/python/PMC/CMakeFiles/_PMCBool.dir/PMCBoolPYTHON_wrap.cxx.o
/home/aakash/gras/build/PMC/python/PMC/PMCBoolPYTHON_wrap.cxx: In
function
'void SWIG_InitializeModule(void)’:
/home/aakash/gras/build/PMC/python/PMC/PMCBoolPYTHON_wrap.cxx:3433:21:
warning: statement has no effect [-Wunused-value]
*

In my opinion this is an assembler issue for armV7, but I’ve got no
leads
on how to solve this. Will mapping this instruction with an equivalent
assembly instruction for armV7 work?

Here’s /proc/cpuinfo
*$ cat /proc/cpuinfo
Processor : ARMv7 Processor rev 2 (v7l)
BogoMIPS : 1001.88
Features : swp half thumb fastmult vfp edsp neon vfpv3
CPU implementer : 0x41
CPU architecture: 7
CPU variant : 0x3
CPU part : 0xc08
CPU revision : 2

Hardware : sun5i
Revision : 0000
Serial : 0000000000000000
*
OS version: Linaro image 13.06
Kernel: linux-sunxi 3.0.62+

Manoj_G · July 26, 2013, 9:30pm

On 07/26/2013 07:57 AM, Manoj G. wrote:

We’ve been successful in building dependencies for gnuradio on armv7
platform, however while building GRAS, we got this error:

This line is probably the culprit.

github.com

captaintrash/theron/blob/master/Include/Theron/Detail/Threading/Utils.h#L163


      
          
          
inline void Utils::Backoff(uint32_t &backoff)
          {
              // The backoff scales from a simple 'nop' to putting the calling thread to sleep.
              // This implementation is based roughly on http://www.1024cores.net/home/lock-free-algorithms/tricks/spinning
              if (++backoff < 10)
              {
                  YieldToHyperthread();
              }
              else if (backoff < 20)
              {
                  for (uint32_t i = 0; i < 50; ++i)
                  {
                      YieldToHyperthread();
                  }
              }
              else if (backoff < 22)
              {
                  YieldToLocalThread();
              }
              else

The thread pools can operate on condition variables or spin locks. For
the spin lock implementation, there is a “pause” instruction –
obviously not applicable on arm. I think you can simply comment this out
to get things rolling.

Supposing this is the issue. What is the recommended fix… just a
simple #ifdef X86_64 around this line?

-josh

Manoj_G · July 27, 2013, 11:19pm

Yes I’ll work on it and send you a patch with conditional preprocessors.

Manoj_G · July 30, 2013, 5:59am

On 07/29/2013 09:08 AM, Manoj G. wrote:

There is no equivalent instruction of pause in ARM that hints the following
loop is a spin-lock loop; However I just mapped pause into NOP and its not
throwing an error (yet)

Wny not only insert the asm for x86 and no code for all other archs.
This patch will break on PPC and other non x86 archs.

Philip

Manoj_G · July 30, 2013, 6:35am

That sounds good.

From: manojgudi [email protected]
Date: Mon, 29 Jul 2013 17:00:35 +0530
Subject: [PATCH] fixed ASM

Include/Theron/Detail/Threading/Utils.h | 7 ++++±-
1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/Include/Theron/Detail/Threading/Utils.h
b/Include/Theron/Detail/Threading/Utils.h
index 8c6baf2…e2811f1 100644
— a/Include/Theron/Detail/Threading/Utils.h
+++ b/Include/Theron/Detail/Threading/Utils.h
@@ -168,8 +168,11 @@ THERON_FORCEINLINE void Utils::YieldToHyperthread()
YieldProcessor();

#elif THERON_GCC

asm volatile (“pause”);

#ifdef arm
```
   __asm__ __volatile__ ("NOP");
```
#elif X86_64
```
      __asm__ __volatile__("pause");
```
#endif

#endif

–
1.7.9.5

Manoj_G · July 30, 2013, 2:12am

There is no equivalent instruction of pause in ARM that hints the
following
loop is a spin-lock loop; However I just mapped pause into NOP and its
not
throwing an error (yet)

Here’s the diff:

diff --git a/Include/Theron/Detail/Threading/Utils.h
b/Include/Theron/Detail/Threading/Utils.h
index 8c6baf2…76947c7 100644
— a/Include/Theron/Detail/Threading/Utils.h
+++ b/Include/Theron/Detail/Threading/Utils.h
@@ -168,8 +168,12 @@ THERON_FORCEINLINE void Utils::YieldToHyperthread()
YieldProcessor();

#elif THERON_GCC

```
  #ifdef __arm__
```
```
  __asm__ __volatile__ ("NOP");
```
```
  #else
```
```
  __asm__ __volatile__("pause");
```
```
  #endif
```

asm volatile (“pause”);

#endif

Can anybody comment on performance degradation?

Manoj_G · July 30, 2013, 10:09am

On 07/29/2013 07:31 AM, Manoj G. wrote:

That sounds good.

I second that. Just ifdef the pause for the fix.

For a little extra information here. The thread pools in Theron can have
different yield strategies. GRAS happens to use by default the condition
variable strategy. So the code in question actually has zero impact at
runtime unless a spin lock yield is requested.

Beyond just compiling, in the near future, we will get to test questions
like. Which strategy works better on arm? And that yield code in
particular, what in particular would be most optimal for arm.

Some relevant links.
http://docs.theron-library.com/5.01/structTheron_1_1Framework_1_1Parameters.html

-josh