Hi,
I’m trying to use the LSB streaming functionality but cant seem to get
the
following code to work:
self.u=usrp2.source_16sc(options.interface)
self.u.set_center_freq(options.freq)
self.u.set_decim(options.decim)
print "Current GPIO State: " + str(self.u.read_gpio())
print "GPIO Streaming: " +str(self.u.enable_gpio_streaming(1))
self.head=gr.head(gr.sizeof_float, 100000)
self.sink=gr.file_sink(gr.sizeof_float, ‘testfile’)
self.connect(self.u,self.head,self.sink)
Looking through the firmware I believe I should be using IO Pin 15 for
the
LSB of I and Pin 14 for the LSB of Q - I can see the bit toggling from
the
print “current GPIO state” statement but opening the captured file in a
hex
editor I cant see any change in the LSB of each int16 regardless of the
level of pin 15/14.
I’m testing with a BasicRX daughterboard and have updated the firmware
to
the latest published binaries.
Am I missing something obvious?
Thanks in advance,
Tim
I’m not sure if the streaming works with the standard firmware. You’ll
probably need to use a special firmware (std_2rxhb_2tx_dig.rbf). I’m
actually using std_2rxint_2tx_dig.rbf, but this is only because I need
a different type of filter (boxcar).
juha
On Mon, Jun 21, 2010 at 10:41, Juha V. [email protected] wrote:
I’m not sure if the streaming works with the standard firmware. You’ll
probably need to use a special firmware (std_2rxhb_2tx_dig.rbf). I’m
actually using std_2rxint_2tx_dig.rbf, but this is only because I need
a different type of filter (boxcar).
GPIO streaming is a standard feature of the libusrp2/gr-usrp2
components and should be working.
Tim–I haven’t looked into it yet, but it’s on my list. It looks like
you are doing the right thing.
Johnathan
Juha,
Do I understand correctly that this is similar to gr-gpio? I thought
VRT allowed separate streams, why are the bits still in the LSB of I
and Q? Does this also work with UHD?
I’m using pre-UHD/VRT code at the moment - my understanding is the
metadata
VRT adds applies to a group of samples, the GPIO streaming lets you get
boolean values associated with specific samples (with some fixed delay)
- I
was planning to use it to get a PPS into the PC before realising I could
just use timestamps…
How about dual DDC? Any news about dual DDC for usrp2? How easy would
it be to add this to UHD?
I was looking into getting two IF streams as I and Q data a few weeks
ago -
there is a version of the USRP2 firmware which supports 2 DDC’s - I
think it
uses slightly different filters - in the USRP2 FPGA code its under
top/u2_rev3_2rx_iad. A mailing list post suggests the Makefiles need
updating to use the new Ethernet code so its probably not suitable for
UHD
yet.
In case its helpful to anyone, the quick solution I went for here (given
I’m
still struggling to get an old version of Xilinx ISE) was to modify the
firmware to set the BasicRX as a quadrature board and tuning to 0, which
disables the CORDIC bit. This gives you two streams of IF if your happy
with
both streams being the same sample rate/untuned.
Tim
On 06/23/2010 05:37 AM, Tim P. wrote:
realising I could just use timestamps…
VRT (the protocol) does handle multiple separate streams. Each stream
is tagged with its stream ID.
How about dual DDC? Any news about dual DDC for usrp2? How easy would
it be to add this to UHD?
Adding a second DDC to the fpga is not hard. The support for this is
not yet in UHD, but will be.
which disables the CORDIC bit. This gives you two streams of IF if your
happy with both streams being the same sample rate/untuned.
You no longer need an old version of ISE. You can use 12 now. Just use
the ise12 branch.
Matt
Oops,
I read that it was usrp1.
Do I understand correctly that this is similar to gr-gpio? I thought
VRT allowed separate streams, why are the bits still in the LSB of I
and Q? Does this also work with UHD?
How about dual DDC? Any news about dual DDC for usrp2? How easy would
it be to add this to UHD?
I am really looking forward to UHD with streaming gpio and dual DDC
functionality.
juha
On Mon, Jun 21, 2010 at 20:23, Johnathan C.