GPIF bus cycle waveform

Hi,

After looking through the FX2 data sheet, the GPIF
designer app’s generated code and your edit_gpif
script output, I (hope) I have an understanding of the
actual data flow bus cycle (I am only focusing on
FIFORd):

You use flow states. There is a flowstate in state S1,
which constantly asserts REN and OE (and BOGUS) while
the transaction has not yet expired.
It deasserts all CTLx signals when the transfer is
complete.

You do data transfers on both edges of IFCLK. the
FLOWSTB register indicates that CTL4 is your master
strobe - is this correct? I thought CTL4 was a reset
signal (CLRST).

I have tried to meet these requirements in my
firmware, but it is a little buggy. I also had a look
at the verilog code (bus_interface.v) to see how your
GPIF signalling works, but only have experience with
VHDL.

To summarise:
OE and REN are active-high, and data is clocked out on
both edges of IFCLK.

What part do the RDYx pins play in the flowstate? Or
do they only affect transitions between S1, S2…S6?

I’m really close to getting this thing working, but
for a clearer understanding of the signalling over the
GPIF.

Thanks again
Kalen


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On Sun, Jul 16, 2006 at 06:40:58PM +0100, Kalen Watermeyer wrote:

the transaction has not yet expired.
at the verilog code (bus_interface.v) to see how your
GPIF signalling works, but only have experience with
VHDL.

To summarise:
OE and REN are active-high, and data is clocked out on
both edges of IFCLK.

Yes, modulo problem with signals being asserted one cycle too long on
either the RD or WR (I don’t remember which it was.)

What part do the RDYx pins play in the flowstate?

None.

Or do they only affect transitions between S1, S2…S6?

Nope, not that either…

I’m really close to getting this thing working, but
for a clearer understanding of the signalling over the
GPIF.

Abandon all hope :wink:
As the cypress docs indicate, a logic analyzer is very useful (read:
required).

Eric

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