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I am a newbie in USRP FPGA programming,
I used once Xilinx ISE to execute some VHDL code, generated a bit file
to
program a Virtex 4,
But now in the context of GNU Radio and USRP. I would like to know what
are
the tools recommended and where can i find the documentation of the FPGA
(I
am using USRP N210),
and I am using Ubuntu Precise 12.04, so what kind of software or kit do
I
have to handle.
What I want to try with the USRP’s FPGA is to send it a stream of
packets
(Header + Payload),
header field’s length being known and fixed in advance, I need the FPGA
to
override a part of the Payload’s field with its time register’s value
and
send the stream after.
Is that possible first then what steps to do ?
All explanations and hints are well appreciated.
Regards,
What I want to try with the USRP’s FPGA is to send it a stream of
packets
(Header + Payload),
header field’s length being known and fixed in advance, I need the
FPGA to
override a part of the Payload’s field with its time register’s
value and
send the stream after.
Is that possible first then what steps to do ?
This is possible. However, you have to be aware: The USRPs are
basically ADCs and DACs on steroids with mixer daughterboards.
So you don’t transfer streams of packets from Host to USRP to get them
onto the ether, you send streams of complex time samples that encode
such packets. So, the USRP does not see packets, it sees streams (or
bursts) of samples. You could of course write some HDL to replace
certain samples in a sample stream with other samples, but then you
would have to do modulation in hardware – this is not really the first
thing I’d try when learnig how to use the FPGA in a USRP.
Thank you for your reply,
What I am aiming ultimately is to estimate the time delay a packet could
have when running through the following path:
HOST(1) =>[Ethernet]=> USRP(1)[FPGA-DAC-AnalogPath-Antenna] ==> On the
air
==> The same path Reversed (USRP(2)) ==> HOST(1) or another HOST,
The problem here is that the time delay of propagation on the air is so
insignificant compared to the time delay of Hardware propagation then
especially through the Ethernet from the Host(1) or to the Host(2),
NEXT, that let’s say software delay (From the moment the packet is
passed
from a modulator block in a gnu radio top block to the USRP Sink to the
moment it is transformed and inserted into the stream to the FPGA) is
VARIABLE, That’s why I asked if it is better to migrate to use FPGA time
domain, by inserting time register’s value into the appropriate field in
the
packet stream,
Am I pursuing a good path or non realistic and infeasible.
Best Regards,