Getting the fpga counter for timestamping

GNU Radio
1

Hi,

I need to know if there is a way to retrieve a counter-like value from
the
FPGA to timestamp the moment I sent a packet.
More precisely, I am sending a stream of packets from the host to radio,
to
be sent to another radio in the Rx side.

Any clarifications are welcome,
Regards,

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2

On 05/07/2013 03:43 PM, NaceurElOuni wrote:

Hi,

I need to know if there is a way to retrieve a counter-like value from the
FPGA to timestamp the moment I sent a packet.
More precisely, I am sending a stream of packets from the host to radio, to
be sent to another radio in the Rx side.

You can actually use stream tags to control the time that a packet is
transmitted

http://code.ettus.com/redmine/ettus/projects/uhd/wiki/GNU_Radio_UHD#Using-UHD-Software-with-GNU-Radio

-josh

3

On 05/07/2013 04:59 PM, NaceurElOuni wrote:

Thank you josh,

I just want to be sure, are stream tags handled by timing of the FPGA (clock
ticks) or the timestamps are being inserted from within the host userspace,
because am getting too much variability on the latency when timestamps are
inserted in the OS.

For transmit: The host generates the timestamps and the samples and
sends this to the FPGA. The FPGA interprets the timestamps and waits
until the exact moment specified by the time to transmit.

The timestamps specify an absolute time on the device, so there isnt
room for variability, the packet with time either arrives before the
scheduled transmission time or its late and wont be transmitted.

This is the case for all the USRP devices except USRP1.

-josh

4

Thank you josh,

I just want to be sure, are stream tags handled by timing of the FPGA
(clock
ticks) or the timestamps are being inserted from within the host
userspace,
because am getting too much variability on the latency when timestamps
are
inserted in the OS.

regards.

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5

The FPGA interprets the timestamps and waits
until the exact moment specified by the time to transmit.

The timestamps specify an absolute time on the device

I would like to know what is the mechanism the FPGA is using to
interpret
the timestamps. You are supposing there is two time references: the
host’s
and the FPGA’s.
Is there a way to read the FPGA’s specific register that is storing the
timestamps or the value of the clock tic or whatever manner to schedule
the
transmission.

Every explanation would be great.
Best regards.

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6

Every explanation would be great.
Best regards.

On the host, you can use an API to set the FPGA time register to
whatever you want:

set_time_now (foo)

Which will cause the FPGAs notion of the TOD to be set to “foo” as soon
as it processes it. From that point forward, the FPGA TOD register is
incremented
every 10 nanoseconds, based on the master clock on the device.

set_time_next_pps (foo)

Which will cause the FPGA to latch in the time “foo” at the next PPS
edge. Just as above, the FPGA TOD register will increment every 10
nanoseconds.

There are also calls to fetch the FPGA TOD register:

get_time_now ()

Which will tell you what the FPGA thought the TOD was at the time the
command was processed.

http://files.ettus.com/uhd_docs/doxygen/html/classuhd_1_1usrp_1_1multi__usrp.html
may be useful

As might this:

http://files.ettus.com/uhd_docs/manual/html/sync.html

–
Marcus L.
Principal Investigator
Shirleys Bay Radio Astronomy Consortium