FX2 Controller/ GPIF questions

Hi All,

Can anyone shed some light on how the FX2 firmware / GPIF handles
simultaneous reads and writes? I mean if I set up my USRP1 to receive
and transmit simultaneously, what is happening exactly down there at
the GPIF level? Given that there are two GPIF waveform configurations
one each for Read and Write, are there two concurrent instantiations
of the FIFO state machine during simultaneous read/ writes for full
duplex operation , or in other words are there separate FIFO state
machines operating in two configurations at the same time? If the GPIF
state machine is in only one configuration (FIFOWr or FIFORd) at one
time, how is true full duplex communication possible?

Thanks,
Arya

On Wed, Feb 16, 2011 at 3:54 AM, Arya S. [email protected]
wrote:

state machine is in only one configuration (FIFOWr or FIFORd) at one
time, how is true full duplex communication possible?

There are separate GPIF waveforms for reads and writes, which occur as
512 byte bursts when data and buffer space are available. FIFO buffers
in both directions allow for full duplex operation.

There’s a good summary of the main run loop on the wiki page.

http://gnuradio.org/redmine/wiki/1/UsrpFAQFX2

Thomas

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