Can anybody help me with this? I need a full schematics of RFX2400, the
one available on gnuradio’s site is not complete!
-------- Original Message --------
Subject: Re: [Discuss-gnuradio] USRP2, is that possible to skip the
Ethernet and pass data through general purpose (physically accessible)
inputs to the FPGA?
Date: Thu, 28 Oct 2010 20:00:53 -0600
From: Malihe A. [email protected]
To: Nick F. [email protected]
Hi Nick,
I actually changed the nsgpio module so that io_tx_06 and io_rx_06 have
fix value and the board is always configured as full duplex but yet the
pin 8 (ENOP, on and off switch for RF output) of the U101( AD8349, the
modulator) is switching on and off and I don’t know which signal is
controlling it (b/c it is not shown in the schematics). Can you please
send me the complete schematics of RFX2400 or tell me how to control pin
ENOP of the U101?
Thanks,
Malihe
Hi Nick,
I had few interesting observation yesterday.
First of all, I followed what you recommended, stock FPGA and firmware
image and the sin wave at TX. looking at the GRC’s FFT, I realized that
the 1.1MHz spike is there but not always, it is choppy, I see either the
spike or white noise! with this setup, I was probing different points on
the RFX2400 db and I found in (please look at the schematic) in U209 pin
1 is always 0 and pin 2 is always 1, but in U202 pin 1 is sometime 0 and
sometime 1 and pin 2 is its complement. that means TX/RX is not always
derived with RF_TX! (and I think that is exactly why the source is
choppy and the received signal is choppy …). Also looking at pin 8
(ENOP, on and off switch for RF output) of the U101( AD8349, the
modulator), I found that pin is sometime 0 and sometime 1 (it seems it
follows the same pattern as pin 2 of U202), but I can’t find what signal
is controlling that pin on the schematics?! do you know which signal it
is? thus my understanding is that the firmware is not translating the
full duplex configuration on the GRC to the correct values on U202 and
101. I’d like to take the control of those signals (io_tx_06 and
io_rx_o6 and whatever else) out of the firmware and fix them in FPGA
code and see what happens! but first Id’ like to know your comments on
these observations.
Thanks,
Malihe