Since I’m not familiar with USB architecture, it might seem like stupid
Now I’m receiving some data(called RxData) from USRP and obviously USRP
set as a receiver mode. At the same time, I have a data to be
transmitted(called TxData) which is not related with received data. The
is that I recognize the end of packet from RxData and manually switch
USRP as a transmit mode. After that, I send TxData to USRP.
As I know, USRP is using EP2 and EP6 as OUT and IN port respectively and
each port is half duplex line. Is it mean that I cannot receive data
from USRP and simultaneouly send data into TXFIFO on FPGA?
I just want to reduce delay between end of received packet and start of
transmit some other packet.
If possible, I want to fill the TXFIFO simultaneously during receiving
from USRP and quickly switch USRP to a transmitter.
Is there any suggetions of reducing delay between receiver and
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