Hi,

after having read several papers on the subject, I am still not able

to find the answer I am looking for. I wonder how to calculate the

frequency resolution of the CORDIC algorithm. In an earlier post to

this mailing list it was stated that the resolution is approximately

0.01 Hz. Could anyone point me to where I can find a deviation of this

result?

## Regards,

Trond D.

On 6/28/07, Trond D. [email protected] wrote:

Hi,

after having read several papers on the subject, I am still not able

to find the answer I am looking for. I wonder how to calculate the

frequency resolution of the CORDIC algorithm. In an earlier post to

this mailing list it was stated that the resolution is approximately

0.01 Hz. Could anyone point me to where I can find a deviation of this

result?

This paper is really good for understanding the CORDIC:

AFS Directories Unavailable

It is specifically written to look at FPGA implementations, which is

nice.

As I understand it, the USRP uses the CORDIC as described in section

3.1 of that paper. A phase accumulator is used to spin the angle

around, and the modulated sin/cos or xi is the output on xo and yo

after 12 iterations of the algorithm. The value of zo should be zero,

and any error leftover should be represented on that output.

The resolution should really be how slowly you can spin the zi

component while maintaining accuracy out of the CORDIC. It may be

that with 12 iterations and 16-bit inputs 0.01 Hz is possible, whereas

more iterations or larger inputs might get better resolution, but I

suspect you’re really past the point of diminishing returns at that

point.

Is that helpful?

Brian

Trond D. wrote:

Hi,

after having read several papers on the subject, I am still not able

to find the answer I am looking for. I wonder how to calculate the

frequency resolution of the CORDIC algorithm. In an earlier post to

this mailing list it was stated that the resolution is approximately

0.01 Hz. Could anyone point me to where I can find a deviation of this

result?

The CORDIC deals with phase, not frequency, so there is no concept of

frequency resolution for it. The one being used in the USRP has 14 bits

of PHASE resolution.

Frequency resolution is controlled by the NCO, or phase accumulator. In

our case it has 32 bits of resolution. 64 MHz/2^32 is your frequency

resolution in Hz.

Matt

Trond D. wrote:

after having read several papers on the subject, I am still not able

to find the answer I am looking for. I wonder how to calculate the

frequency resolution of the CORDIC algorithm. In an earlier post to

this mailing list it was stated that the resolution is approximately

0.01 Hz. Could anyone point me to where I can find a deviation of

this result?

The “phase generator” part of the CORDIC block works by incrementing a

32-bit phase register by a fixed amount per clock cycle. The full size

of the register represents 2*PI() of phase, or one cycle of the

waveform. The user programmed phase increment per clock cycle then

represents frequency.

In the receive chain of the FPGA, the phase generator is clocked at 64

MHz. Thus, the minimum delta-frequency (a one bit change in the phase

increment register) is 64 MHz / pow(2, 32) = 0.0149 Hz.

Thus, for DC, the phase increment value is zero, for 0.0149 Hz, it is 1,

for 0.0298 Hz, it is 2, all the way up to 32 MHz, where it is pow(2,

31). You can also tune negative frequencies, where -1 creates -0.0149

Hz, etc.

The CORDIC block then uses the resulting “sawtooth” phase value to

rotate the incoming signal by that amount, resulting in complex

frequency conversion.

Did this help, or confuse?

–

Johnathan C.

Corgan Enterprises LLC

http://corganenterprises.com

2007/6/28, Johnathan C. [email protected]:

32-bit phase register by a fixed amount per clock cycle. The full size

31). You can also tune negative frequencies, where -1 creates -0.0149

Hz, etc.

The CORDIC block then uses the resulting “sawtooth” phase value to

rotate the incoming signal by that amount, resulting in complex

frequency conversion.

Did this help, or confuse?

Thanks a lot! This was indeed the last missing piece in my CORDIC

puzzle, which by no means covers the entire picture, but a sufficient

subset for my humble needs

–

Trond D.

2007/6/28, Johnathan C. [email protected]:

Thus, for DC, the phase increment value is zero, for 0.0149 Hz, it is

1,

for 0.0298 Hz, it is 2, all the way up to 32 MHz, where it is pow(2,

31). You can also tune negative frequencies, where -1 creates -0.0149

Hz, etc.

There is one more thing that I just can not figure out. The largest

angular rotation that can be performed by the CORDIC is +/- pi/2,

which means that is takes four cycles to rotate the vector all the way

around. How come the largest frequency that can be generated be 32

MHz.

Thanks in advance

##
Regards,

Trond D.

2007/6/28, Brian P. [email protected]:

This paper is really good for understanding the CORDIC:

The resolution should really be how slowly you can spin the zi

component while maintaining accuracy out of the CORDIC. It may be

that with 12 iterations and 16-bit inputs 0.01 Hz is possible, whereas

more iterations or larger inputs might get better resolution, but I

suspect you’re really past the point of diminishing returns at that

point.

Is that helpful?

Thank you a lot for your reply. I have already read the mentioned

paper, and found it useful.

##
Regards,

Trond D.

Trond D. wrote:

around. How come the largest frequency that can be generated be 32

MHz.

If you look in the cordic.v file you will see that the actual CORDIC is

preceded by some logic which rotates by 0, 90, 180, or 270 degrees.

Matt