Free USRP FPGA Resources

[EngSFiras]

Dear Matt,
Dear All,

Is the DDC decimate by 2 half band filter built inside the FPGA ? If it
is
so, then how much the free available FPGA resources left after building
all
the present USPR circuits in it? I mean, is there a free space to modify
the
CIC + HBF circuit and to build a complete DDC block (CIC + CFIR + PFIR)
?

Thank you in advance.

Firas

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[EngSFiras]

On 4/22/07, Eng. Firas [email protected] wrote:

Dear Matt,
Dear All,

Is the DDC decimate by 2 half band filter built inside the FPGA ? If it is
so, then how much the free available FPGA resources left after building all
the present USPR circuits in it? I mean, is there a free space to modify the
CIC + HBF circuit and to build a complete DDC block (CIC + CFIR + PFIR) ?

The standard USRP build has about 95% of the LE’s used up, but a
decent amount of memory free. If you plan on using only 1 complex RX
path and 1 complex TX path - you can remove quite a bit of logic and
build with a single side enabled.

Thank you in advance.

Firas

Brian

[EngSFiras]

Brian P. wrote:

all

Thank you Brian.

Best regards,
Firas

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