On 1/30/07, Roberto M. firstname.lastname@example.org wrote:
has someone of you ever used SynplifyDSP tool (Synplicity) or System
Since the USRP uses an Altera Cyclone FPGA, you should be checking out
their DSP Builder software - found here:
(NOTE: Requires MATLAB w/ Simulink)
How can the generated code (with previous tools) interact
with the VHDL code already being in the USRP normal working?
The code generated by those systems would just be another
instantiation within the FPGA project. It could probably hook up
between the FIFOs that are used for shuffling the data around, but
Matt would be the authority to really check with.