Hello folks. I am currently looking at using the USRP for interaction
with RFID tags. The crux of the problem is that I need to transmit a
continuous carrier wave to power the tag, but I also need very low
latency with respect to receiving a tag signal and responding to that
signal (< 500us. Not going to happen, but the closer the better).
Currently, I am transmitting the carrier from the host which eats up
half of my USB bandwidth and keeps the TX buffers full, both of which
are killing my latency.
My question is, would it be possible to modify the FPGA so that the
default behavior is to transmit the carrier until it receives buffers
for transmit? This should reduce the latency by using the USB half
duplex, keeping the TX buffers empty which allows for burst transmits,
and also by freeing up some computes which are now burned sending out
To further complicate the problem, I’ve very little experience
working with FPGAs and verilog. So, a caveat to the above question is
that this not only needs to be possible, it needs to be relatively
straight forward as well.
Any advice as to the feasibility of this endeavor would be greatly
appreciated. If it seems reasonable, pointers as to what would be
involved, where I would need to look, etc. would also be helpful.