Am I right to state that the fpga firmware is configured as followed:
Tx chain (0 to 2 possible)
- NCO fine+coarse on Analog Devices Chip
- low-pass 4x interpolation on AD-Chip
- CIC interpolation filters, separate for I- and Q-Data
Cordic turned off, internal DUC (duc.v) turned off?
And RX Chain (0 to 4 possible)
- Cordic for downconversion
- CIC decimator per I- and Q-Stream
- Halfbandfilter, after CIC, per I/Q-Stream
DDC not used? (I mean, ddc.v)
Low-pass decimation filter on AD-Chip disabled.
I wonder if http://gnuradio.org/trac/wiki/UsrpRfxDiagrams is still