I was just wondering if anyone tried to create a vector waveform file
(.vwf) to simulate the usrp FPGA in quartus. At first glance it seemed
to me that there would be too many signaIs to reproduce, but is it
possible/viable?
Regards
Lance
I was just wondering if anyone tried to create a vector waveform file
(.vwf) to simulate the usrp FPGA in quartus. At first glance it seemed
to me that there would be too many signaIs to reproduce, but is it
possible/viable?
Regards
Lance
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