On Dec 19, 2007 9:22 AM, [email protected] wrote:
I’m working on FPGA and in particulary on side RX. I want to insert a filter FIR
pass band after the output of ADC and before the input of DDC. The filter is
simulated across MATLAB in particulary across “fdatool” and it is written in
verilog. What’s the sampling frequency for this filter FIR? Is correct to
insert this filter?
The sample rate of the ADC is 64Msps. The samples then go through the
CORDIC to generate complex pairs, then through a CIC with minimum
decimation of 4, and then through a halfband 2:1 decimating filter.
What symbol rate are you looking at in your simulation and how many
samples per symbol are you looking to process? What are the
characteristics of your filter (taps, symmetric, etc?)
The lack of hardware multipliers inside the FPGA requires you to run a
relatively simple filter unless you are running at “low” sample rates
which allows you to serialize the data going through one or two
multipliers and accumulate the output.