FIFO size and duplex mode

Hi!
We are considering the possibility of bying a couple of USRP boards
for building the MIMO 2 RX 2 TX duplex system.

  1. For us it is critical to know the precise size on FIFO buffers. So
    we could evaluate overrun / underrun probabilities.

Matt said it is 2K lines. Does it mean 2048 bits?

  1. Does the board work in time division duplexing of frequency division
    duplexing mode?
    From the schematic I tend to think it works in TDD mode.

Could someone, please, confirm this?

The answers to these questions are very important for us, because we
want to make sure the USRP is suitable for our needs.

Andrey A wrote:

Hi!
We are considering the possibility of bying a couple of USRP boards
for building the MIMO 2 RX 2 TX duplex system.

  1. For us it is critical to know the precise size on FIFO buffers. So
    we could evaluate overrun / underrun probabilities.

Matt said it is 2K lines. Does it mean 2048 bits?

No, it means 2K lines. Each line is 32 bits.

  1. Does the board work in time division duplexing of frequency division
    duplexing mode?
    From the schematic I tend to think it works in TDD mode.

both, but fdd operation requires a lot of frequency separation.

Matt

On Wed, Oct 03, 2007 at 04:15:41AM -0700, Matt E. wrote:

No, it means 2K lines. Each line is 32 bits.

The FX2 also implements quad buffering in both TX and RX directions.
Each buffer is 512 bytes.

If you run your app with real-time scheduling enabled, then the real
question becomes “do you have enough CPU cycles on the host” to keep
up.

Eric

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