External 1pps pulse


#1

Hello,

I currently have four complex input signals coming in through USB and I
have a 1pps timing pulse coming from a gps source that I need to
synchronize the 64MHz clock to and also pass on to the PC so that I know
exactly which sample it occurred on. Can someone give me some guidance
as to how I might accomplish this?

Thank you,
Hans


#2

On Fri, Mar 16, 2007 at 01:08:27PM -0700, Hans G. wrote:

Hello,

I currently have four complex input signals coming in through USB
and I have a 1pps timing pulse coming from a gps source that I need
to synchronize the 64MHz clock to and also pass on to the PC so that
I know exactly which sample it occurred on. Can someone give me
some guidance as to how I might accomplish this?

Thank you,
Hans

Hi Hans,

In the good news / bad news department, the good news is that this
shouldn’t be hard to do with the “inband signaling” work that’s
currently underway. The bad news is that this work probably won’t
be ready for a couple of months.

In the interim, if you’re willing to steal an LSB, you could modify
the verilog such that it reported the presence or absence of the 1pps
in the LSB of say, the I component of the first channel.

Eric


#3

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#4

Hi Hans,
Eric

Hi Eric,

Thanks for the reply. I could use an LSB on one signal, although I hate
to
lose a whole bit when I only have 12 to start with. I was hoping there
might be a way to interleave another signal in with the four complex
ones
I’m receiving in the PC. My data rate is fairly low, so another signal
would not hurt much. I haven’t looked at the Verilog code yet. Would
a
fifth interleaved signal even be implement in the context of the verilog
code? Also, what method would you use to receive the 1pps signal so the
verilog code could stick it into an LSB, or another signal?

The other issue is synchronizing the 64MHz clock to the 1pps. Is there
any
way to do this synch with the usrp’s onboard clock, or will I have to
make
an external clock?

Thanks,
Hans


#5

Hans G. wrote:

Hi Hans,
Eric

Hi Eric,

Thanks for the reply. I could use an LSB on one signal, although I
hate to lose a whole bit when I only have 12 to start with.

It would be 1 bit out of 16, not out of 12. We send 16 bit samples over
the bus.

I was hoping there might be a way to interleave another signal in with
the four complex ones I’m receiving in the PC. My data rate is fairly
low, so another signal would not hurt much. I haven’t looked at the
Verilog code yet. Would a fifth interleaved signal even be implement
in the context of the verilog code? Also, what method would you use
to receive the 1pps signal so the verilog code could stick it into an
LSB, or another signal?

This is also possible. You could put in into another channel. See the
code in tx_buffer.v

The other issue is synchronizing the 64MHz clock to the 1pps. Is
there any way to do this synch with the usrp’s onboard clock, or will
I have to make an external clock?

You’ll need to use an external clock.

Matt