Error of mapping when rebuild FPGA

with command
gnuradio/usrp2/fpga/top/u2_rev3$ make bin

I got errors when mapping:
ERROR:Pack:2310 - Too many comps of type “RAMB16” found to fit this
device.
ERROR:Pack:18 - The design is too large for the given device and
package.

below is design summary…

Design Summary:
Number of errors: 2
Number of warnings: 36
Logic Utilization:
Number of Slice Flip Flops: 12,620 out of 40,960 30%
Number of 4 input LUTs: 18,605 out of 40,960 45%
Logic Distribution:
Number of occupied Slices: 12,449 out of 20,480 60%
Number of Slices containing only related logic: 12,449 out of
12,449 100%
Number of Slices containing unrelated logic: 0 out of
12,449 0%
*See NOTES below for an explanation of the effects of unrelated
logic.
Total Number of 4 input LUTs: 19,316 out of 40,960 47%
Number used as logic: 17,464
Number used as a route-thru: 711
Number used for Dual Port RAMs: 32
(Two LUTs used per Dual Port RAM)
Number used as Shift registers: 1,109

The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.

Number of bonded IOBs: 307 out of 333 92%
IOB Flip Flops: 271
IOB Master Pads: 3
IOB Slave Pads: 3
Number of RAMB16s: 44 out of 40 110%
(OVERMAPPED)
Number of MULT18X18s: 16 out of 40 40%
Number of BUFGMUXs: 6 out of 8 75%
Number of DCMs: 1 out of 4 25%

Average Fanout of Non-Clock Nets: 3.35

Peak Memory Usage: 706 MB
Total REAL time to MAP completion: 2 mins 26 secs
Total CPU time to MAP completion: 37 secs

Thank you for any advices!!!

Liang

On Wed, Dec 02, 2009 at 10:06:41PM +0800, 周亮 wrote:

with command
gnuradio/usrp2/fpga/top/u2_rev3$ make bin

Matt can say more about this, but he’s currently at the SDR Forum.
Please note that we’ve been using ISE 10.1 SP3(?) not 11.* to build
it. In our experience, the xilinx tools “leave something to be
desired…”

Can you try it with 10.1 with the latest service pack?

I got errors when mapping:
ERROR:Pack:2310 - Too many comps of type “RAMB16” found to fit this device.
ERROR:Pack:18 - The design is too large for the given device and package.

Eric