Disabling the USRP FPGA HBF


#1

Dear Matt,
Dear Eric,

Is there away to disable (or bypass) the USRP FPGA DDC half band filter?
I
want to get the samples directly from the CIC decimation filter and do
the
low pass filtering by software. I developed a MATLAB based professional
100KHz bandwidth digital down converter as shown in the attached m file.
I
want to test this design in USRP. In the mean time, I cannot do this
because
I don’t have access to the CIC output samples because of the HBF.
Waiting for your help, thank you.

Firas.

http://www.nabble.com/file/8491/testddc100k.m testddc100k.m

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#2

On Thu, May 17, 2007 at 08:18:13AM -0700, Eng. Firas wrote:

Waiting for your help, thank you.

Firas.

http://www.nabble.com/file/8491/testddc100k.m testddc100k.m

If receive only is OK, you can use the 4rx_0tx.rbf fpga configuration.

u = usrp.source_c(0, fpga_filename=“std_4rx_0tx.rbf”)

Eric