I am running into a USB bandwidth issue. I’m sampling data
simultaneously from 2 daughter boards at a decimation rate of 10.
This produces 2*6.4 MS/s * 4 bytes/I and Q sample = 48 MB/s. My
application requires one board to have a decimation rate of 10, but
the other can have a decimation rate of ~30. My understanding of the
USRP is that you cannot easily (i.e. in software) use different
decimation rates for different daughter boards on the same USRP. My
questions are: 1.) Is this easy to do at the FPGA level? 2.) Has
anyone tried this before?
Prof. Brent M. Ledvina
Space @ Virginia Tech
Wireless @ Virginia Tech
643 Whittemore Hall
Bradley Department of Electrical and Computer Engineering
Blacksburg, VA 24061
Office Hours: M 1-2, T 1-3