Hi,
I am running into a USB bandwidth issue. I’m sampling data
simultaneously from 2 daughter boards at a decimation rate of 10.
This produces 2*6.4 MS/s * 4 bytes/I and Q sample = 48 MB/s. My
application requires one board to have a decimation rate of 10, but
the other can have a decimation rate of ~30. My understanding of the
USRP is that you cannot easily (i.e. in software) use different
decimation rates for different daughter boards on the same USRP. My
questions are: 1.) Is this easy to do at the FPGA level? 2.) Has
anyone tried this before?
Regards,
Brent
Prof. Brent M. Ledvina
Assistant Professor
Space @ Virginia Tech
Wireless @ Virginia Tech
643 Whittemore Hall
Bradley Department of Electrical and Computer Engineering
Virginia Tech
Blacksburg, VA 24061
ph: 540.231.0656
Office Hours: M 1-2, T 1-3
Brent M. Ledvina wrote:
Hi,
I am running into a USB bandwidth issue. I’m sampling data
simultaneously from 2 daughter boards at a decimation rate of 10. This
produces 2*6.4 MS/s * 4 bytes/I and Q sample = 48 MB/s.
Actually, the correct calculation of data rate is:
6.4 MS/s * 2 * 2 = 25.6MB/s
One factor of 2 is for I and Q. The other is for 2 bytes per sample,
since 16 bit samples are sent over the USB. They are converted to
floats on the host computer.
My application requires one board to have a decimation rate of 10, but
the other can have a decimation rate of ~30. My understanding of the
USRP is that you cannot easily (i.e. in software) use different
decimation rates for different daughter boards on the same USRP. My
questions are: 1.) Is this easy to do at the FPGA level? 2.) Has
anyone tried this before?
It is not possible with the default FPGA build to use different rates
for 2 RX streams. The TX and RX can have different rates though.
Matt
On Sep 4, 2007, at 2:11 PM, Matt E. wrote:
6.4 MS/s * 2 * 2 = 25.6MB/s
One factor of 2 is for I and Q. The other is for 2 bytes per sample,
since 16 bit samples are sent over the USB. They are converted to
floats on the host computer.
So, for two daughter boards, I’d expect twice your calculation: 51.2
MB/s.
In your judgement, how challenging is it to modify the FPGA build? I
could tolerate hardwired decimation rates.
Matt
Prof. Brent M. Ledvina
Assistant Professor
Space @ Virginia Tech
Wireless @ Virginia Tech
643 Whittemore Hall
Bradley Department of Electrical and Computer Engineering
Virginia Tech
Blacksburg, VA 24061
ph: 540.231.0656
Office Hours: M 1-2, T 1-3
Brent M. Ledvina wrote:
Actually, the correct calculation of data rate is:
6.4 MS/s * 2 * 2 = 25.6MB/s
One factor of 2 is for I and Q. The other is for 2 bytes per sample,
since 16 bit samples are sent over the USB. They are converted to
floats on the host computer.
So, for two daughter boards, I’d expect twice your calculation: 51.2
MB/s.
Yes, that is correct.
In your judgement, how challenging is it to modify the FPGA build? I
could tolerate hardwired decimation rates.
You need to come up with some sort of packing order for the data, and
then unpack in the host. The changes won’t be hard, but debugging will
be…
It is possible that the inband signaling may make this easier.
Matt