Hi,
In our application we need to emit pure tones on two RFX400
daughtercards sitting on the same USRP board. More importantly, the
phase of the two RF carriers need to be in sync or should have a
deterministic difference.
I put together a simple experiment (GnuRadio 3.1 release branch r8117,
USRP rev 4.5, FLEX400 10-11-05) which sends a pair of constant signals
to the USRP in the baseband. The RF transmit outputs are directly
connected to a scope (5GS/s, 50 ohm imp.). My problem is that the
phase relationship between the two sines is random and changing every
time I run the python script. I suspected that the DUC(s) in the CODEC
chip(s) cause this, so I was trying to “turn them off” by modifying
db_flexrf.py (self.set_lo_offset(0)) and using carriers where the
RFX400 board can tune to without the help of the DUC. I verified with
two LFTX boards that the CODECs “generate” constant outputs.
Still, the RF waves have random phases, which I cannot explain (since
the PLLs on the daughtercards are “driven” by the same clock coming
from the USRP).
Since I have very limited RF background, I need you to explain this
and/or suggest a solution for the initial problem.
Thank you.
–
peter
Peter Volgyesi wrote:
phase relationship between the two sines is random and changing every
time I run the python script. I suspected that the DUC(s) in the CODEC
chip(s) cause this, so I was trying to “turn them off” by modifying
db_flexrf.py (self.set_lo_offset(0)) and using carriers where the
RFX400 board can tune to without the help of the DUC. I verified with
two LFTX boards that the CODECs “generate” constant outputs.
Still, the RF waves have random phases, which I cannot explain (since
the PLLs on the daughtercards are “driven” by the same clock coming
from the USRP).
The RFX400s have PLL chips on them. The PLL chips on the 2 boards are
fed the same reference clock since it comes from the motherboard.
However, they both divide the clock down by the “R Divider” value, which
is typically 8. The RFX400 has a second divide-by-2 as well for a
total of 16. Thus there would be an 8-way ambiguity, since the dividers
could be at different phases. Thus the relative phases between 2 boards
can only be one of 16 discrete values. This value will stay constant as
long as you don’t retune to a different frequency or allow the pll
enable pin to go low.
If you set your RF frequency to a multiple of 64 MHz, however, there
will be no ambiguity.
Matt
Suprin, Charles E. wrote:
Your comments above confused me.
Looking at http://www.gnuradio.org/trac/wiki/USRPClockingNotes, it
claims that the cards use their own crystal oscillators. Wouldn’t the
above change require hardware changes on the Flex400 board and changing
the firmware?
Or has the documentation not caught up with the hardware?
The docs needed updating. I did a quick change to the docs, let me know
if it isn’t clear enough.
Thanks,
Matt
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On Jun 2, 2008, at 3:20 PM, Matt E. wrote:
If you set your RF frequency to a multiple of 64 MHz, however, there
will be no ambiguity.
What of the above is {the same, different} for the RFX2400’s?
I’m using Rev 4.2 USRPs with RFX2400 Rev 30s. Presumably with Rev 4
USRPs but older RFX2400s with 64 MHz oscillators I could make the mods
necessary to use the FPGA refclk.
- -Dan
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Dan H. wrote:
ambiguity, since the dividers could be at different phases. Thus the
relative phases between 2 boards can only be one of 16 discrete
values. This value will stay constant as long as you don’t retune to
a different frequency or allow the pll enable pin to go low.
If you set your RF frequency to a multiple of 64 MHz, however, there
will be no ambiguity.
What of the above is {the same, different} for the RFX2400’s?
The 2400s don’t have the extra divide by 2.
I’m using Rev 4.2 USRPs with RFX2400 Rev 30s. Presumably with Rev 4
USRPs but older RFX2400s with 64 MHz oscillators I could make the mods
necessary to use the FPGA refclk.
Yes.
Matt