Newb here. I’m wondering what you are using for a design flow to
produce
fpga code? I assume you are obtaining verilog? What tools are used to
produce the verilog and work with it?
On Wed, Feb 27, 2008 at 8:07 AM, Neal B. [email protected]
wrote:
Newb here. I’m wondering what you are using for a design flow to produce
fpga code? I assume you are obtaining verilog? What tools are used to
produce the verilog and work with it?
All Verilog source is written by hand - no HDL generators are being
used.
The USRP uses an Altera Cyclone part and Quartus II for synthesis.
The upcoming USRP2 will have a Xilinx Spartan 3E (I believe) part and
will use WebPack/XST for synthesis.
Brian
On Wed, Feb 27, 2008 at 9:13 AM, Neal B. [email protected]
wrote:
Thanks!
I just grabbed webpack and I’m trying it out.
One thing you might like to know:
In my initial testing, it’s working on Fedora F8 x86_64. It doesn’t want
you to run on x86_64, but with a few minor hacks it’s working so far.
Documenting said hacks on the Wiki would be wonderful!
http://gnuradio.org/trac/wiki
Brian
On Wed, Feb 27, 2008 at 09:29:11AM -0500, Brian P. wrote:
http://gnuradio.org/trac/wikiBrian
Instructions on making it work on FC6 through 8 here:
http://gnuradio.org/trac/wiki/ISEonFC6
Eric
Brian P. wrote:
will use WebPack/XST for synthesis.
Brian
Thanks!
I just grabbed webpack and I’m trying it out.
One thing you might like to know:
In my initial testing, it’s working on Fedora F8 x86_64. It doesn’t
want
you to run on x86_64, but with a few minor hacks it’s working so far.