Delay through dsp pipeline

Hello,
In several discussions, I recall it was mentioned that the timestamp
reference is at the end of the dsp pipeline. Is the dsp pipeline
consisting just of the DDC or anything else?
It was also mentioned that the delay through the dsp pipeline depending
on some factors such as decimation rate. If we have multiple usrps2
using the same decimation rate, center freq, what other factors would
contribute to the difference in arrival of the signal at the end of the
dsp pipeline? (if two usrps2 are receiving from the same antenna and
using a 10MHZ gps reference signal).
Is there a way to figure out the delay from the ADC to end of the dsp
pipeline?
I also saw a mention about a patch for the start_rx_stream_at, which
tells the usrps2 to start streaming at a specific time. Can someone
elaborate on that some more? Whose time does the usrp2 based on to do
that, and does that ensure two usrp2 start streaming at the same time?
Thanks for any inputs!
Thanh

Hi,

The DDC in the dsp_rx pipeline is build with several filters. Depending
on the decimation rate you choose different filter configurations. See
the FAQ regarding DDC and decimation values.

I guess you want to sample the source from the antenna synchronous in
both usrp2s. The case is the that the dsp_core_rx is reset at start up
of the usrp2. So the receiver will start to fill their pipeline at
different points of time. To get rid of this problem we have used the
1PPS-signal to reset the DDC in both usrp2 at the same point of time.
Take a look in the dsp_core_rx.v file.

To start receiving the samples synchronous we then just polled the
timestamp and when we received a sample with timestamp = 0 we started
our process.

-Patrik E.


FrÃ¥n: d[email protected]domain.invalid
[mailto:d[email protected]domain.invalid] För
Pham, Thanh
Skickat: den 12 augusti 2009 21:45
Till: [email protected]
Ämne: [Discuss-gnuradio] delay through dsp pipeline

Hello,
In several discussions, I recall it was mentioned that the timestamp
reference is at the end of the dsp pipeline. Is the dsp pipeline
consisting just of the DDC or anything else?
It was also mentioned that the delay through the dsp pipeline depending
on some factors such as decimation rate. If we have multiple usrps2
using the same decimation rate, center freq, what other factors would
contribute to the difference in arrival of the signal at the end of the
dsp pipeline? (if two usrps2 are receiving from the same antenna and
using a 10MHZ gps reference signal).
Is there a way to figure out the delay from the ADC to end of the dsp
pipeline?
I also saw a mention about a patch for the start_rx_stream_at, which
tells the usrps2 to start streaming at a specific time. Can someone
elaborate on that some more? Whose time does the usrp2 based on to do
that, and does that ensure two usrp2 start streaming at the same time?
Thanks for any inputs!
Thanh

Patrik-thanks for your response.
I was wondering if the “1PPS signal to reset the DDC” capability has
been implemented in the current firmware yet? If I call a sync_to_pps
function, does that cause the ddc to reset at the pps edge?
If it has not been implemented in the current fpga firmware, would
someone who has done this be able to share the firmware image with me? I
don’t have the resource and tool to be able to recompile the code for
the fpga.
Thanks a bunch!
Thanh

From: Patrik E. [mailto:[email protected]]
Sent: Thursday, August 13, 2009 12:39 AM
To: Pham, Thanh; [email protected]
Subject: Re: delay through dsp pipeline

Hi,

The DDC in the dsp_rx pipeline is build with several filters. Depending
on the decimation rate you choose different filter configurations. See
the FAQ regarding DDC and decimation values.

I guess you want to sample the source from the antenna synchronous in
both usrp2s. The case is the that the dsp_core_rx is reset at start up
of the usrp2. So the receiver will start to fill their pipeline at
different points of time. To get rid of this problem we have used the
1PPS-signal to reset the DDC in both usrp2 at the same point of time.
Take a look in the dsp_core_rx.v file.

To start receiving the samples synchronous we then just polled the
timestamp and when we received a sample with timestamp = 0 we started
our process.

-Patrik E.


FrÃ¥n: d[email protected]domain.invalid
[mailto:d[email protected]domain.invalid] För
Pham, Thanh
Skickat: den 12 augusti 2009 21:45
Till: [email protected]
Ämne: [Discuss-gnuradio] delay through dsp pipeline
Hello,
In several discussions, I recall it was mentioned that the timestamp
reference is at the end of the dsp pipeline. Is the dsp pipeline
consisting just of the DDC or anything else?
It was also mentioned that the delay through the dsp pipeline depending
on some factors such as decimation rate. If we have multiple usrps2
using the same decimation rate, center freq, what other factors would
contribute to the difference in arrival of the signal at the end of the
dsp pipeline? (if two usrps2 are receiving from the same antenna and
using a 10MHZ gps reference signal).
Is there a way to figure out the delay from the ADC to end of the dsp
pipeline?
I also saw a mention about a patch for the start_rx_stream_at, which
tells the usrps2 to start streaming at a specific time. Can someone
elaborate on that some more? Whose time does the usrp2 based on to do
that, and does that ensure two usrp2 start streaming at the same time?
Thanks for any inputs!
Thanh

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