I think 3.3V LVTTL and LVCMOS are really the same.
They’re the same only different.
For most purposes, the differences don’t matter too much. The biggest difference is in the output drive capability. LVTTL outputs are required to be able to source/sink 2mA while remaining compliant while LVCMOS outputs are only required to source/sink 100uA.
For those interested in the “official” word, refer to the actual JEDEC standard:
From a Xilinx FPGA point of view, compared to LVTTL, 3.3V LVCMOS:
-is slightly faster
-has some hysteresis (about 100 mV)
-allows more pins to be in LVCMOS mode at any one
time, given same drive strength
-has no difference in output or sink current
capabilities (as opposed to the JEDEC mention)
For the OP, it would probably be wise to use LVCMOS, as it appears to be
flexible; you can also select 2.5V and 1.8V signaling levels without
These notes come from the Spartan 3 (being used on the new USRP). I’m
things are similar with Altera equivalents.