Default FPGA I/O standard

Hi all,

I am trying to find out the default I/O standard e.g LVTTL, LVCMOS that
is set on the FPGA general purpose debug pins (16-bits available on the
daughter card connectors). I don’t have Quartus II installed yet. Is
there a way to find out or set this through Python?

Thanks,
Nirali P.
DSP Application Engineer
Coherent Logix

Nirali P. wrote:

Hi all,

I am trying to find out the default I/O standard e.g LVTTL, LVCMOS that is set on the FPGA general purpose debug pins (16-bits available on the daughter card connectors). I don’t have Quartus II installed yet. Is there a way to find out or set this through Python?

3.3V LVCMOS

Hi Matt,

I modified the usrp_std.v file to make connections to the debug IO pins
and
then on my PC tried to compile the project using Quartus II software.
The
compile went successfully, but later when I opened the Pin-Out file
under
Compilation Report all the signals showed at 3.3V-LVTTL. I had only
clicked
on the play button after opening the .qpf project.
I would like to know if the default settings are still all 3.3V LVCMOS
and I
inadvertently changed something. If not, I would like to set the 16-bit
debug pins to LVCMOS since I am trying to attach a CMOS cable to the
pins on
basic RX. Could you recommend a way to do this? Do I have to look at IO
banking rules etc.? I have some FPGA background but not a whole lot.

Thanks,
Nirali P.

Nirali P. wrote:

basic RX. Could you recommend a way to do this? Do I have to look at IO
banking rules etc.? I have some FPGA background but not a whole lot.

I think 3.3V LVTTL and LVCMOS are really the same.

Matt

On Wed, Sep 26, 2007 at 04:56:24PM -0500, Nirali P. wrote:

Hi all,

I am trying to find out the default I/O standard e.g LVTTL, LVCMOS
that is set on the FPGA general purpose debug pins (16-bits
available on the daughter card connectors). I don’t have Quartus II
installed yet. Is there a way to find out or set this through
Python?

3.3V CMOS

Eric

I think 3.3V LVTTL and LVCMOS are really the same.

Matt

According to this:

http://www.interfacebus.com/voltage_LV_threshold.html

They are, indeed, basically the same.

Brian

They’re the same only different.

For most purposes, the differences don’t matter too much. The biggest
difference is in the output drive capability. LVTTL outputs are required
to be able to source/sink 2mA while remaining compliant while LVCMOS
outputs are only required to source/sink 100uA.

For those interested in the “official” word, refer to the actual JEDEC
standard:

http://www.jedec.org/download/search/jesd8c.pdf

On 10/1/07, Matt E. [email protected] wrote:

I think 3.3V LVTTL and LVCMOS are really the same.

Matt

According to this:

http://www.interfacebus.com/voltage_LV_threshold.html

They are, indeed, basically the same.

Brian

Thanks everyone for the help and information. I also discovered that if
you
want to increase the drive strength for any IO standard for the FPGA IO
pins
it is possible through the Assignment Editor in Quartus II under Logic
Options by setting current_strength_new to

Thanks again for all the information.
Nirali

I think 3.3V LVTTL and LVCMOS are really the same.

They’re the same only different.

For most purposes, the differences don’t matter too much. The biggest difference is in the output drive capability. LVTTL outputs are required to be able to source/sink 2mA while remaining compliant while LVCMOS outputs are only required to source/sink 100uA.

For those interested in the “official” word, refer to the actual JEDEC standard:

http://www.jedec.org/download/search/jesd8c.pdf

From a Xilinx FPGA point of view, compared to LVTTL, 3.3V LVCMOS:

-is slightly faster

-has some hysteresis (about 100 mV)

-allows more pins to be in LVCMOS mode at any one
time, given same drive strength

-has no difference in output or sink current
capabilities (as opposed to the JEDEC mention)

For the OP, it would probably be wise to use LVCMOS, as it appears to be
more
flexible; you can also select 2.5V and 1.8V signaling levels without
changing pin
assignments.

These notes come from the Spartan 3 (being used on the new USRP). I’m
assuming
things are similar with Altera equivalents.

-Jeff

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