Decimate by 2 possible?

Hi,

I am using the TV_RX and USRP to capture the 64 Msps data from the A/D
converter and send that to another downstream board for processing. I am
connecting the signal from the ADC to the debug IO pins of the FPGA to
get
to the 16 io_rx[] pins of Basic RX. However, my board-to-board
interconnection turned out to have a bandwidth limitation of 50 MHz so I
can
no longer hope to send 64 Msps raw data from the ADC over the
interconnect
bus. The next best thing would be to decimate by a factor of 2 and then
route the 32 Msps data to the debug pins. I understand the the CIC has a
decimation range of [4,5,6,.128] and the HBF decimates by a factor of 2.
Is
there a way to get an overall decimation of just 2 by possibly bypassing
the
CIC and using only the HBF? If this sounds like a dumb question then,
what
would be the best way to get 32 Msps over to the Basic RX card using
what’s
already in the FPGA?

Thanks in advance for any suggestions.

Nirali

On 10/22/07, Nirali P. [email protected] wrote:

there a way to get an overall decimation of just 2 by possibly bypassing the
CIC and using only the HBF? If this sounds like a dumb question then, what
would be the best way to get 32 Msps over to the Basic RX card using what’s
already in the FPGA?

Thanks in advance for any suggestions.

Is there a reason you want to play directly with 32Msps? What is your
target symbol rate? Do you need all that bandwidth, or do you just
need a portion of it? Usually when there is a bandwidth limitation of
50MHz, and since a square wave is composed of all odd harmonics of the
fundamental, then 32MHz would really need a couple odd harmonics to
get through pretty reliably, shouldn’t it?

Maybe it would be better if you decimated to 1x or 2x the symbol rate
and then processed that data on your other board?

You can change the halfband coefficients to make it a symbol matched
filter instead of a generic halfband filter if you’d like.

What do you think? Is this more plausible of a scenario for you?

Brian

Brian,

Thanks for your response.

What is your target symbol rate?

My target symbol rate is 10.76 MHZ (8-vsb ATSC symbol rate). I need only
2x
of this symbol rate, i.e 21.52 Mhz to do down stream processing.

Is there a reason you want to play directly with 32Msps?
Only for troubleshooting interpolation-algorithm problems on the
downstream
board.
If I send a lower rate e.g 8Msps then there is a need for interpolation
first and it appears that there is a bug in the algorithm for cubic
interpolation method on the downstream board that causes sampling
offsets.
So it would be nice if there was only downsampling involved in getting
to
21.52 Mhz.

Maybe it would be better if you decimated to 1x or 2x the symbol rate
and then processed that data on your other board?
Yes, you are right. Ultimately I should only send the decimated data.
If I use both the CIC and HBF then the lowest combined decimation rate
is 8,
which gives me 8 Msps output. I might avoid the HBF for now and get a
decimation of 4 in the CIC. I found from an earlier post that the file
4rx_0tx.rbf has only CIC and no HBF. Do you know how this file can be
generated? I need to start at the toplevel in order to make connections
to
the debug IO pins.

What do you think? Is this more plausible of a scenario for you?
This definitely makes good sense. Thanks for the suggestions!

Nirali P.

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