DC offset problem on OOK modulation

Hi all,

Now I’m working on OOK modulation/demodulation with RFX2400 d’board.
I modified dbpsk.py and psk.py in order to get [1+0j , 0+0j] baseband
signal and verified this signal is sending to USRP board. Since I’m
using tx
amplitude=14000, the range is [+14000,0] in real axis.

But, I read this post releated with OOK modulation.


I cannot understand DC offset problem. As I know, the signal we transmit

s(t) = sqrt(2)SI(t)cos(2pifct) - sqrt(2)SQ(t)sin(2pifct);

SI(t) and SQ(t) are the baseband signal we are feeding from PC to USRP,
range is [-32767,32767].

In OOK modulation, SI(t)=+14000 or 0, and SQ(t)=0 assuming that I do not
RRC filter.
This signal will be passing through CIC in FPGA and feeded into AD9862.
After that, it will be upconverted to carrier frequency. But after DUC,
might still be signed data. So I’m still confused of what the DC offset
problem is.

I have two questions,

  1. Is it true that all bit streams handled in FPGA are signed data?

  2. If yes, why do we experience DC offset problem? And in which stage is