DBSRX and clock spurs

On Thu, Mar 11, 2010 at 12:27 PM, John O. [email protected]

Hi all,
We’ve been doing some development work with the DBSRX on a USRP1
recently. We’ve noticed fairly strong clock spurs while running
usrp_fft.py, occurring every 64 MHz (strangely, both even and odd
harmonics of the ref clock on the USRP) over the oprerating range of
the board.
Has anyone else made the low-pass filter modification with success?
Are there any other options for managing these spurs? Obviously on
wide-band receivers like the DBSRX, it is tough to provide a decent
solution that handles the spurs in all cases. I’m starting to think
they may simply be radiating from the USRP into the DBSRX, in which
case I’d assume low-pass filtering wouldn’t help. Any guidance here
would be appreciated.

Hi John,

We’ve seen the same problem here, both on the USRP1 and on an old
version of our own product; spurs showing up at harmonics of the ADC
clocking frequency.

In my investigations of our system, I narrowed the source down to the
ADC clock and data lines, which were actually radiating with enough
power to be picked up by our RF amplifiers (the price you pay when
shooting for sensitivity < -110dBm). Unfortunately, our solution is a
whole new motherboard design with the handling of such issues in mind,
including aggressive RF shielding.

As stopgap solutions, we found that clocking our ADC slower helped
(the radiating traces aren’t nearly as good antennas at low
frequencies), as would shielding problem traces (ADC clock and data
lines, and sensitive RF lines). A fair amount of tweaking and
optimizing our RF and downconverter circuitry gave us some results as
well, but not enough to really ignore those spurs.

Hope this helps,

Patrick Yeon
613.369.5104 x418

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