We’ve been doing some development work with the DBSRX on a USRP1
recently. We’ve noticed fairly strong clock spurs while running
usrp_fft.py, occurring every 64 MHz (strangely, both even and odd
harmonics of the ref clock on the USRP) over the oprerating range of
the board. These spurs are measured to be, at worst, ~40 dB above the
noise floor, or -70 dBm, calibrated against a tone also being
received, with a gain setting of 30 on the usrp_fft.py plot. We used
a freq of 1089 MHz for our measurements (with the spur showing up 1
MHz off at 1088 MHz). I did some digging through old posts for the
discussion board, and found the following report of a similar issue:
The follow-up to this post indicates that there is a low-pass filter
on the DBSRX (R193+C261, and R195+C262) that could potentially reduce
the clock spur power. We’ve made the suggested modification to
increase both C261 and C262 to reduce the cutoff frequency of the
low-pass filter, but this didn’t seem to make any difference in the
performance. Looking more closely, we checked the DBSRX’s clock
source, and it has the default resistor position (R193 is populated),
so it is taking its clock from io_rx_00, which is a 4 MHz clock coming
from the FPGA. The 64 MHz clock is still coming on to the board
through clock_p, but goes right into a DNP resistor.
Has anyone else made the low-pass filter modification with success?
Are there any other options for managing these spurs? Obviously on
wide-band receivers like the DBSRX, it is tough to provide a decent
solution that handles the spurs in all cases. I’m starting to think
they may simply be radiating from the USRP into the DBSRX, in which
case I’d assume low-pass filtering wouldn’t help. Any guidance here
would be appreciated.
Our DBSRX is from rev 2.2, dated 2007.