Daughterboard clocking on USRP2

Hi all,
Just looking through the WBX daughterboard code in the latest git repo
for adding support for the USRP2 (which can be found at
usrp2/firmware/lib/). I noticed that in adf4350.c, there is a #define
for INPUT_REF_FREQ that is defined as 50e6 (50 MHz), which is then
used in all of the follow-on calculations for determining register
settings. I had thought that the USRP2 only provided a 100 MHz ref
clock for use by the daughterboards on the clock_rx_p line, but I must
be missing a divide by 2 some place. Can anyone confirm A) if the WBX
runs off of 50 or 100 MHz, and B) if it is 50 MHz, how the clk div 2
occurs on the USRP2?

Thanks much…


Regards,
John O.
CEO/System Architect
Epiq Solutions
www.epiq-solutions.com

runs off of 50 or 100 MHz, and B) if it is 50 MHz, how the clk div 2
occurs on the USRP2?

The adf4350 has a ref clock doubler and ref clock divider bit, in
addition to the R divider setting. In the case of WBX on USRP2, we use
the ref clock divider bit (adf4350_regs.c, line 34, adf4350_regs_rdiv2),
hence the 100M clock is divided to 50M on the adf4350 before the R
divider.
Ahh…gotcha. Makes sense now.

I could have written the INPUT_REF_FREQ more clearly, my apologies for
the confusion.
No worries. I just wanted to make sure I wasn’t missing something.
Thanks for the quick response Jason.


Regards,
John O.
CEO/System Architect
Epiq Solutions
www.epiq-solutions.com

On Tue, Mar 16, 2010 at 04:34:44PM -0500, John O. wrote:

occurs on the USRP2?
The adf4350 has a ref clock doubler and ref clock divider bit, in
addition to the R divider setting. In the case of WBX on USRP2, we use
the ref clock divider bit (adf4350_regs.c, line 34, adf4350_regs_rdiv2),
hence the 100M clock is divided to 50M on the adf4350 before the R
divider.

I could have written the INPUT_REF_FREQ more clearly, my apologies for
the confusion.

Jason

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