DAC I/Q swap and bit inversion

Esteemed Colleagues,

Many thanks to the members of this community that my responded to my
previous query. They were most helpful. I will have you know that the
status
of my endeavor of sending SMS messages over CDMA has accumulated
momentum
and my determination escalates with every passing milestone. I have
never
been one to quit on a challenge.

I’m wondering if someone out there can further explain this rather
perplexing segment in the top level verilog code. It appears that I and
Q
signals have been swapped, and that one rail has had the bits inverted.
The
comment “inverted to facilitate clean layout” causes me sleepless nights
and
minor bouts of indigestion. Why is this bit inversion performed? As I
have
modified the transmit path and send my own 2’s complement data, shall I
keep
this inversion in the code or is it to conform only to something done in
the
default FPGA build? Also, why is the negative edge of the clock used?

wire [15:0] dac_a_int, dac_b_int;
// DAC A and B are swapped in schematic to facilitate clean layout
// DAC A is also inverted in schematic to facilitate clean layout
always @(negedge dsp_clk) DACA <= ~dac_b_int;
always @(negedge dsp_clk) DACB <= dac_a_int;

Much appreciation to any helpful tidbits which the group can contribute
to
remedying this quandary.

Cheers,
Reginald

Reginald,
Here’s what’s going on:
Firstly what would be nominally “DAC A (port1)” and “DAC B (port2)” in
the AD9777 (by Analog Devices definition) are used for the opposite for
the opposite signals by the USRP/ETTUS definition i.e USRP signal DACB
is actually processed by physical DACA.
Next (only) Port 1 on the DAC had the analog differential outputs
swapped w.r.t the downstream circuit and so the USRP compensates
digitally by inverting the DACA signal. (Matt, this just occurred to me,
you should be 2’s comping the bus here, not simply inverting it, you’ve
introduced an LSB DC offset).
This is of course all done in the name of getting an optimal PCB layout
for the analog signals out of the DAC’s as the comments indicate.

-Ian

p.s The negative edge of the clock is used here because the DAC uses the
positive edge, it gives nice setup and hold margin.

On Wed, Oct 12, 2011 at 4:12 PM, Ian B. [email protected]
wrote:

(Matt, this just occurred to me, you should be 2’s comping the bus here,
not simply inverting it, you’ve introduced an LSB DC offset).

An optimization – the 1 LSB offset is swamped by real offset in the
hardware, so we just take it out as part of normal DC offset
calibration.

Matt

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