I am interested in loading a custom FPGA image onto the USRP2. I have
been looking through the schematics and code. Basically, I want to
clarify what happens when the USRP2 is powered up. Please correct
anything that I am missing.
There is an SD card that has two images, one for aeMB and one for FPGA.
There is a Xilinx CPLD that interfaces the SD card to the Spartan 3
FPGA. When power is applied, the CPLD accesses the SD card. When the
FPGA is ready, the CPLD begins to load firmware onto the FPGA. This is
where I am getting confused. I believe the CPLD first loads the aeMB
firmware onto the FPGA. Once it is loaded, aeMB takes over and pulls the
FPGA image from the SD card. Is this process correct?
Another question has to do with the i2C EEPROM on the motherboard. I
have read that this chip stores a small program that puts the board in a
low-power state and blinks LEDs in a ceratin way. Is this what it does
on the USRP2? So at what point does this program get loaded onto the
FPGA and at what point does this program lose control to the firmware
that is getting loaded onto the FPGA?
Lastly, during my experiments loading custom FPGA images, is there
anyway I could risk “bricking” the unit? The SD card can of course be
re-loaded, so I am not worried about that. There is internal
non-volatile memory in the CPLD, but that can only be modified by
connecting a 4-wire programming interface which I am not going to do.
Also there is the on-board EEPROM. Is there any way that I could mess up
the EEPROM which would brick the unit?
Any help in understanding these question is greatly appreciated!