I’m looking at using the FPGA on the USRP to improve the performance in
what my lab is doing. To learn about the Verilog code already written
FPGA, I’m trying to do phase recovery with the Costas loop at the end of
rx_chain. First of all, is this a good project? It may not be good to
in the codebase for general purpose gnuradio since it’s only relevant
certain protocols, but is there anything wrong with this approach that
brain dead? I’ve read that the FPGA is using 90% of its logic cells
current implementation, and that turning off a tx_chain or an rx_chain
solve that problem, but I’m not there yet.
I’ve been hacking at it for a bit, and I drafted up a simple vlog file
and a slightly modified rx_chain here:
I’m new to FPGAs and signals (So why am I working on this? To learn.),
have a few questions.
I need to store the phase shift somewhere as I correct the guess with
error term. I assume that the phase accumulator in phase_acc.v needs to
something similar, but I don’t understand how it stores its information.
The original C implementation of costas loop has two error terms you
((sample.real()>0 ? 1.0 : -1.0) * sample.imag() -
(sample.imag()>0 ? 1.0 : -1.0) * sample.real());
I chose the simpler because it involved one less multiply, and I didn’t
understand what the other was doing. The point of software radio is to
you to make these decisions in software, but if I had to hardcode one in
FPGA, which would it be? I’m definitely not complicating this further
trying to get that info via USB.
For alpha and beta, I was just going to use a bitshift to scale the
term. That’d also be hardcoded in the vlog code, but what would
constants be? I’ve seen this question asked before, and I looked at the
and it said alpha is around 0.01 or less, so I figure a bitshift by
makes alpha about 1/128, or 0.0078125, and the paper doesn’t mention
beta, so I
said eight places.
What’s the difference between the code in
gr_costas_loop_cc.cc? They seem to do the same stuff, but maybe they’re