Anyone here implemented freq/phase correction and symbol timing
correction in USRP’s FPGA?
Recently I implemented Costas loop and Muller & Mueller algorithm in RTL
by referring the gnuradio code. Now I’m testing it on FPGA. I can get
correct demodulated data(DQPSK) at initial few thousand symbols. After
that I’m getting all rubbish data.
I think the problem with my RTL implementation is not good enough
bit-resolution (unlike implementation on PC). Currently I’m using
15-bits resolution for decimal part. Anyone has any suggestion ?
Anyone here implemented freq/phase correction and symbol timing
correction in USRP’s FPGA?
Recently I implemented Costas loop and Muller & Mueller algorithm in RTL
by referring the gnuradio code. Now I’m testing it on FPGA. I can get
correct demodulated data(DQPSK) at initial few thousand symbols. After
that I’m getting all rubbish data.
I think the problem with my RTL implementation is not good enough
bit-resolution (unlike implementation on PC). Currently I’m using
15-bits resolution for decimal part. Anyone has any suggestion ?
At high SNR, a single bit is probably enough in the detector and 15
bits
in the phase accumulator is also likely more than enough. The error, in
my
opinion, is elsewhere.
No, but I am very interested
From your original post it might seem that fresh eyes might hit the
spot.
I’m more of a VHDL guy, so I might not be too much of a help.
I just thought that others might have a better chance of helping if they
could see the code.
At high SNR, a single bit is probably enough in the detector and 15
bits in the phase accumulator is also likely more than enough. The
error, in my opinion, is elsewhere.
Anyone here implemented freq/phase correction and symbol timing
correction in USRP’s FPGA?
Recently I implemented Costas loop and Muller & Mueller algorithm in RTL
by referring the gnuradio code. Now I’m testing it on FPGA. I can get
correct demodulated data(DQPSK) at initial few thousand symbols. After
that I’m getting all rubbish data.
I think the problem with my RTL implementation is not good enough
bit-resolution (unlike implementation on PC). Currently I’m using
15-bits resolution for decimal part. Anyone has any suggestion ?
At high SNR, a single bit is probably enough in the detector and 15
bits in the phase accumulator is also likely more than enough. The
error, in my opinion, is elsewhere.
Anyone here implemented freq/phase correction and symbol timing
correction in USRP’s FPGA?
Recently I implemented Costas loop and Muller & Mueller algorithm in RTL
by referring the gnuradio code. Now I’m testing it on FPGA. I can get
correct demodulated data(DQPSK) at initial few thousand symbols. After
that I’m getting all rubbish data.
I think the problem with my RTL implementation is not good enough
bit-resolution (unlike implementation on PC). Currently I’m using
15-bits resolution for decimal part. Anyone has any suggestion ?