I’ve got a question regarding the cordic on the usrp. I’ve read up a
lot about how it works. Apparently we get approximately a bit of
accuracy per iteration, so a 12 iteration (included with the normal
usrp fpga build) should give us close to 72dB of dynamic range. I did
some simulations in icarus verilog to verify this. The results are
attached. The signals are all mixed down from 20MHz to 100kHz.
6M.jpg is a 6MHz wide chirp, 150kHz.jpg is a 150kHz wide chirp and
sine is just a sine wave.
The funny thing is, the larger the bandwidth of the signal, the worse
the dynamic range after the cordic becomes. Might this be a
simulation mistake from my side, or is this what happens in the
cordic? I ran another simulation with a 6MHz chirp where I increased
the number of stages of the cordic to 15. The result is the same.
Does anyone have any suggestions? Maybe increasing the bit widths in
I want to get as much of the ADC’s dynamic range as possible. If the
current cordic configuration does this, I’m happy. I use a usrp build
with two IQ RX paths and no TX, so there is some space on the fpga
left for improving the cordic if I need to.
Thanks in advance.