Compile fpga code error

Hi all, I use Qartus II version 9.1 web edition to compile fpga code,
meet a
lot of error.
I enter “D:\fpga\usrp1\toplevel\usrp_inband_usb” then open
“usrp_inband_usb.qpf” then I compile this project. error below:

Error (10054): Verilog HDL File I/O error at adc_interface.v(3): can’t
open
Verilog Design File “…/…/firmware/include/fpga_regs_common.v”
Error (10054): Verilog HDL File I/O error at adc_interface.v(4): can’t
open
Verilog Design File “…/…/firmware/include/fpga_regs_standard.v”
Error (10170): Verilog HDL syntax error at adc_interface.v(31) near text
“)”; expecting “.”, or an operand
Error (10170): Verilog HDL syntax error at adc_interface.v(34) near text
“)”; expecting “.”, or an operand
Error (10170): Verilog HDL syntax error at adc_interface.v(36) near text
“)”; expecting “.”, or an operand
Error (10170): Verilog HDL syntax error at adc_interface.v(38) near text
“)”; expecting “.”, or an operand
Error (10170): Verilog HDL syntax error at adc_interface.v(40) near text
“)”; expecting “.”, or an operand
Error (10170): Verilog HDL syntax error at adc_interface.v(53) near text
“)”; expecting “.”, or an operand
Error (10112): Ignored design unit “adc_interface” at adc_interface.v(6)
due
to previous errors
Error (10054): Verilog HDL File I/O error at io_pins.v(22): can’t open
Verilog Design File “…/…/firmware/include/fpga_regs_common.v”
Error (10054): Verilog HDL File I/O error at io_pins.v(23): can’t open
Verilog Design File “…/…/firmware/include/fpga_regs_standard.v”
Error (10170): Verilog HDL syntax error at io_pins.v(42) near text “:”;
expecting an operand
Error (10170): Verilog HDL syntax error at io_pins.v(44) near text “:”;
expecting “endcase”
Error (10170): Verilog HDL syntax error at io_pins.v(46) near text “:”;
expecting “endcase”
Error (10170): Verilog HDL syntax error at io_pins.v(48) near text “:”;
expecting “endcase”
Error (10112): Ignored design unit “io_pins” at io_pins.v(25) due to
previous errors
Error (10170): Verilog HDL syntax error at master_control.v(42) near
text
“)”; expecting “.”, or an operand
Error (10170): Verilog HDL syntax error at master_control.v(50) near
text
“)”; expecting “.”, or an operand
Error (10170): Verilog HDL syntax error at master_control.v(51) near
text
“)”; expecting “.”, or an operand
Error (10170): Verilog HDL syntax error at master_control.v(88) near
text
“)”; expecting “.”, or an operand
Error (10170): Verilog HDL syntax error at master_control.v(89) near
text
“)”; expecting “.”, or an operand
Error (10170): Verilog HDL syntax error at master_control.v(90) near
text
“)”; expecting “.”, or an operand
Error (10170): Verilog HDL syntax error at master_control.v(91) near
text
“)”; expecting “.”, or an operand
Error (10170): Verilog HDL syntax error at master_control.v(93) near
text
“)”; expecting “.”, or an operand
Error (10170): Verilog HDL syntax error at master_control.v(105) near
text
“:”; expecting an operand
Error (10170): Verilog HDL syntax error at master_control.v(107) near
text
“:”; expecting “endcase”
Error (10170): Verilog HDL syntax error at master_control.v(109) near
text
“:”; expecting “endcase”
Error (10170): Verilog HDL syntax error at master_control.v(111) near
text
“:”; expecting “endcase”
Error (10170): Verilog HDL syntax error at master_control.v(120) near
text
“)”; expecting “.”, or an operand
Error (10170): Verilog HDL syntax error at master_control.v(121) near
text
“)”; expecting “.”, or an operand
Error (10170): Verilog HDL syntax error at master_control.v(122) near
text
“)”; expecting “.”, or an operand
Error (10170): Verilog HDL syntax error at master_control.v(124) near
text
“)”; expecting “.”, or an operand
Error (10170): Verilog HDL syntax error at master_control.v(125) near
text
“)”; expecting “.”, or an operand
Error (10170): Verilog HDL syntax error at master_control.v(126) near
text
“)”; expecting “.”, or an operand
Error (10170): Verilog HDL syntax error at master_control.v(128) near
text
“)”; expecting “.”, or an operand
Error (10054): Verilog HDL File I/O error at rx_buffer.v(25): can’t open
Verilog Design File “…/…/firmware/include/fpga_regs_common.v”
Error (10054): Verilog HDL File I/O error at rx_buffer.v(26): can’t open
Verilog Design File “…/…/firmware/include/fpga_regs_standard.v”
Error (10170): Verilog HDL syntax error at rx_buffer.v(66) near text
“)”;
expecting “.”, or an operand
Error (10112): Ignored design unit “rx_buffer” at rx_buffer.v(28) due to
previous errors
Error (10054): Verilog HDL File I/O error at usrp_inband_usb.v(26):
can’t
open Verilog Design File “…/…/…/firmware/include/fpga_regs_common.v”
Error (10054): Verilog HDL File I/O error at usrp_inband_usb.v(27):
can’t
open Verilog Design File
“…/…/…/firmware/include/fpga_regs_standard.v”
Error (10170): Verilog HDL syntax error at usrp_inband_usb.v(198) near
text
“)”; expecting “.”, or an operand
Error (10170): Verilog HDL syntax error at usrp_inband_usb.v(299) near
text
“,”; expecting “.”, or an operand
Error (10170): Verilog HDL syntax error at usrp_inband_usb.v(426) near
text
“)”; expecting “.”, or an operand
Error (10112): Ignored design unit “usrp_inband_usb” at
usrp_inband_usb.v(29) due to previous errors
Error: Quartus II Analysis & Synthesis was unsuccessful. 45 errors, 35
warnings
Error: Quartus II Full Compilation was unsuccessful. 47 errors, 35
warnings

You need to change the locations of the Verilog files in the code, as
the compiler cannot find them…

~Jeff

On 7/21/2010 4:57 AM, John Wu wrote:

Hi all, I use Qartus II version 9.1 web edition to compile fpga code,
meet a lot of error.
I enter “D:\fpga\usrp1\toplevel\usrp_inband_usb” then open
“usrp_inband_usb.qpf” then I compile this project. error below:
Error (10054): Verilog HDL File I/O error at adc_interface.v(3): can’t
open Verilog Design File “…/…/firmware/include/fpga_regs_common.v”
Error (10054): Verilog HDL File I/O error at adc_interface.v(4): can’t
open Verilog Design File “…/…/firmware/include/fpga_regs_standard.v”


~Jeffrey L., K1VZX

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