CIC Interpolator Filter in the FPGA



i have read that the interplation rate set in the GNU Radio Python
script is
actually a combination of 2 interpolation rate values on the USRP. the
AD9860 chips are set by default to interpolate at a value of 4.
the user must select an interpolation rate that is divisible by 4.

can anyone explain how implemented the CIC interploator Filter (how many
stages) in the FPGA. if we want a interpolation of 32, the interpolation
rate is 4 in the AD9860 (4x interpolation), sothat the interpolation is
32/4=8 in the FPGA (stages ??), am i right?

thanks a lot!


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