I’m looking for opinions about whether doing a single-stage, N=2
decimator in software is practical for
sample rates of ~100Msps. Assume reasonably-modern X86-64 hardware,
and R=[2…500].
It looks like the integrator stage could be reasonably lightweight, and
the comb stage for N=2 could also be
quite lightweight.
Assume that input words are 10 to 12 bits.
It looks like bit growth wouldn’t be much of an issue, because it’s
single-stage.
–
Marcus L.
Principal Investigator
Shirleys Bay Radio Astronomy Consortium
On Sat, Apr 16, 2011 at 7:23 PM, Marcus D. Leech [email protected]
wrote:
It looks like bit growth wouldn’t be much of an issue, because it’s
single-stage.
–
Marcus L.
Principal Investigator
Shirleys Bay Radio Astronomy Consortium
http://www.sbrac.org
My guess is that, yes, you can probably get those speeds from a CIC in
software. You’re right, it’s not very complicated, so, considering other
numbers I’ve seen on various other SDR stuff people have done, I think
it’s
doable. You might have to resort to SIMD programming to really get
there,
though. Then again, that’s what Volk is for 
Tom
I’m looking for opinions about whether doing a single-stage, N=2
decimator in software is practical for
sample rates of ~100Msps. Assume reasonably-modern X86-64
hardware, and R=[2…500].
Assuming you can get the data into the processor fast enough, I
expect you will.
(As a reference point: a decade ago I wrote a fourth order fixed
point Bessel filter as a speedtest for my StrongARM-based SDR
platform, with 16bit input, 32bit coefficients and 64bit accumulator.
After a minor fixup to make it 64-bit clean, it shows a throughput
of >290Msps (fixp) / >275Msps (floatp) on my vanilla Core i7-920.)
Good luck,
JDB.
LART. 250 MIPS under one Watt. Free hardware design files.
http://www.lartmaker.nl/