Changing UHD buffer to avoid latency in Benchmark_tx.py and benchamrk_rx.py

I designed a hopping Primay transmitter changing few lines of Benchmark
tx/rx pythob files.

Now to synchronize I am having a predefined table of frequency hops on
both
the Receiver and transmitter.

I count the packet no at both Rx and Tx and shift to a higher frequency
on
every multiple of 100 packets.

With start there is fully correct reception of packets till 39 on
receiver
side and while the packet count was 39 on receiver side it was above 100
on
transmitted side which means transmitter has hopped to the nearby
channel
and receiver was still waiting for packet count to increase which did
not
happened.

Is this delay between packets arrival ie 39 wrt >100 of transmitted due
to
the buffer size of UHD ?

Or it’s due to PHY layer calculations and processing time?

How do I make it robust to hopping?

I have plans of FHSS synch algos but am trying if these methods work
since
benchmark_rx.py is very strong and rated code in itself.

Jay Prakash
Senior Undergraduate
Electronics Engineering