Carrier sense on USRP


#1

Hello…
i am wondering how carrier sense could be implemented on USRP…
can those PLLs on FPGA be brought to some use?

Can I do something on the lines of takeing running average
Will constantly keep a track of the incoming samples of the received
signals…
calcuate the running average and
Will decide some noise floor/threshold for decision…

I hve very less knowledge of digital signal processing…
will this idea work?

thanks,
amit


#2

On Fri, Apr 21, 2006 at 07:54:58PM -0400, amit malani wrote:

I hve very less knowledge of digital signal processing…
will this idea work?

No need for PLLs, just compute something like RMS power.
Also, though you could do it in the FPGA, you could also do it on the
host.

Eric