I’ve managed to store a sample set on the FPGA and transmit it
periodically. The problem I’m experiencing is that the transmitted pulse
is shorter than what I expected.
I worked out that by setting an interp value of 500 from python, that
the FPGA interpolator would basically be set to 125 to go with the
AD9860s x4. This would mean that to obtain a total rate of 32
Msamples/sec to the DAC, the data rate of the I and Q channels would
have to be 16 Msamples/sec each, and thus 128 000 samples/sec each into
the txchain modules. This should mean that if I provide a samples set of
128 I samples, and 128 Q samples, I should get 1 msec worth of complex
Is this correct? I’m not sure if I overlooked something. The result I
get when monitoring the output is about 750 microseconds instead of
1 msec. Is there perhaps something I didn’t take into account in the
calculations? If anyone can assist it would be greatly appreciated.