Bypassing the interpolation


I think I may not be the first to ask this but here is my problem.

I am designing a radar receiver using a USRP2. My transmits and receives
are done in pulses. The problem is that I require 80MHz bandwidth and
USRP2 can only reach 25MHz. I understand that this is due to to the
limitation of the GB ethernet. I would like to bypass the DDC and then
make it not real time to allow the data to be transmitted as I do not
require the system to be realtime.

My questions are:

  1. Where should I be looking, in the VHDL or the USRP2 firmware to
    to allow full bypass?


  1. I am still trying to understand how to receive on time. Any examples
    refer to?

Cheaw Wen Guey
Research Officer


I am working on a similar project to use a USRP 1 as a RADAR device for
a temperature measurement application. I am not sure about the USRP2,
but for USRP1 it is possible to send a signal from the FPGA to the DACs
without interpolation through manipulation of the FPGA registers and by
using custom verilog code. The most relevant example would be
usrp_radar_mono. I am not sure if there is similar code for the USRP2.


On 8/2/2010 10:59 AM, Cheaw Wen Guey wrote:

Cheaw Wen Guey
Research Officer

~Jeffrey L., K1VZX

~Jeffrey L., K1VZX

By modifying the FPGA you can get rid of the interpolators or
decimators. You can also turn off the interpolate-by-4 function of the
DAC itself if you want to, by modifying the settings of the DAC.