Is there any way to bypass the CIC and the HBF on the USRP N200 to just
stream decimated (no integration) real samples off the 100 MHz ADC? I’d
like to eg., record every 25th sample arriving on the ADC. I’d like to
avoid compiling my own fpga is necessary.
Is there any configuration of calc_cic_filter_word and
calc_cordic_word_and_update in the firmware that would magically do
You could only do that by modifying the FPGA. It would be a very minor
mod, though. Hook up the undecimated ADC values to where the output of
decimators go, and leave everything else intact. Then just set the
decimators as normal and you will get the rate you request.
I did manage to sample two real channels at 25 MHz! I set the NCO to 0
the mux to “A:AB”. I don’t know why I didn’t think of this trick
Now the real part is channel 0 and and imaginary part channel 1. I will
next try to do the fpga mod. Can you point me to the correct file in the
fpga? I’d like to take a stab at this.
The reason why I’m doing this, is I’m exploring the possibility of using
the N200 as a phase comparator. We are looking for picosecond scale
variations, and I’m trying to do all the calculations in double
floating point to avoid phase inaccuracies caused by integer arithmetic.
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