Bus widths and data rates

Hello,

I have been trying to understand the tx and rx data paths through the
AD9862
and the FPGA (standard configuration).

RX side:

  • The two ADCs of the AD9862 push data onto two 12 bit buses

  • After the FPGA MUX the 16 bit I/Q signals pass into the assigned DDC

  • Are four extra bits assigned to the received I/Q when they arrive
    onto
    the FPGA?

TX side:

  • The 16 bit I/Q signals pass into the FPGA demux and arrive at the
    appropriate AD9862 chip

  • I/Q signals arrive interleaved on a 14 bit bus into the AD9862

  • Are the I/Q signals truncated by 2 bits before they are sent onto the
    14
    bit bus?

Thanks,

Tomas

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On Jan 30, 2008 9:35 AM, TomasOMaille [email protected] wrote:

  • After the FPGA MUX the 16 bit I/Q signals pass into the assigned DDC

  • Are four extra bits assigned to the received I/Q when they arrive onto
    the FPGA?

Pretty much. In the DC offset removal process, they are assigned on
input. Here is where it happens:

http://gnuradio.org/trac/browser/gnuradio/trunk/usrp/fpga/sdr_lib/adc_interface.v#L34

You can see that the input of the rx_dcoffset module is assigned:

.adc_in({adc0[11],adc0,3'b0})

Which is a 1 bit sign extension, the 12 original bits, then 3 bits of
0’s.

TX side:

  • The 16 bit I/Q signals pass into the FPGA demux and arrive at the
    appropriate AD9862 chip

  • I/Q signals arrive interleaved on a 14 bit bus into the AD9862

  • Are the I/Q signals truncated by 2 bits before they are sent onto the 14
    bit bus?

Yes, as can be seen here:

http://gnuradio.org/trac/browser/gnuradio/trunk/usrp/fpga/toplevel/usrp_std/usrp_std.v#L179

Whatever 16-bits are coming from the tx_chain module is truncated by
2-bits and sent out the DACs.

Brian

On Wed, Jan 30, 2008 at 06:35:07AM -0800, TomasOMaille wrote:

Hello,

I have been trying to understand the tx and rx data paths through the AD9862
and the FPGA (standard configuration).

Hi Tomas,

Take a look here

http://www.gnuradio.org/trac/wiki/UsrpRfxDiagrams

and ask again if you’re still got questions.

Eric

Thanks Brian,

That clears up a lot in my head.

My Verilog knowledge is pretty primitive at this point.

Tomas O’Maille

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