Building USRP2 FPGA on ISE 11.4

GNU Radio
1

I was able to place and route the design on ISE 11.4 using a ‘high’
effort
and ensuring that the speed grade selected is -5 (that really made a
difference of about 20MHz in the speed of the final design). However,
when
it comes time to generate the bitstream, it complains about the -g
Match_cycle:Auto and insists on changing it to -g Match_cycle:NoWait,
and
then throws an error, with no information.

Does this ring a bell for anyone? I haven’t seen it before.

Thanks,
TMB

2

Tracey-

I was able to place and route the design on ISE 11.4 using a ‘high’ effort
and ensuring that the speed grade selected is -5 (that really made a
difference of about 20MHz in the speed of the final design). However, when
it comes time to generate the bitstream, it complains about the -g
Match_cycle:Auto and insists on changing it to -g Match_cycle:NoWait, and
then throws an error, with no information.

You didn’t have to change any source files or the constraints file? No
coregen errors?

-Jeff

3

Nope, Nope, and Nope. I was rather shocked, things never go that well
for me
:slight_smile:

I pulled the u2_rev3 and just resolved my way through the source tree. I
was
not expecting it to generate cleanly. I did regenerate two cores as part
of
the process, dumped a couple of the generated .v files because they
refused
to resolve properly, but the first time through they regenerated and
went
right through place and route with no errors, and no timing issues like
I
had with it earlier (set to the -4 speed grade).

I just havent been able to generate the bitstream, and I won’t have a
chance
to do any testing til next week, if I do get it resolved.

Tracey

4

On Mon, Feb 15, 2010 at 6:59 PM, Tracey B. [email protected]
wrote:

I just havent been able to generate the bitstream, and I won’t have a chance
to do any testing til next week, if I do get it resolved.

Just for another data point, on 64 bit linux running ISE 11.4, I
pulled directly from git, did “touch <…>/coregen/*”, and make proj,
make synth, then make bin in u2_rev3, and got a bit file okay. Bitgen
gave an info message about the Match_cycle change, but otherwise just
normal warnings about dangling ram pins and built the bit file just
fine (although I haven’t actually tested it on the usrp2 yet).
There were some warnings about deprecated options in the project early
on, but they seemed more or less harmless.

I’m not sure how your coregen cores got regenerated. ISE 11.4 has
fifo generator 5.3, while the .xco files in coregen/* are for version
4.3 (which is why I had to touch all those files so it wouldn’t try to
rebuild them, but just use the existing .ngcs)

Jared