Thank you Eric, Roshan, Brian, Achilleas, Eenrti for your earlier help!
I have been going through the verilog code and my observations till now
been that digital downconversion and some amount of decimation are
implemented in the FPGA in receive path. I was trying to see if there is
receiver functionality that could be pushed into the FPGA? I wanted to
such a block into the FPGA, that does not use USB bus much to
with other receiver blocks and result in USB bus bandwidth gain. I am
clear as to which block would be the best suited for this? Any comments
Also, I am of the opinion that there would be certain blocks which can
smart/efficient use of FPGA features/power as opposed to being
as C++ block on general purpose processor. Any help with this one?
If there is a common block for both the above questions, then I would
to start with that and implement on the FPGA.