Bandwidth Across USB


#1

I know this is probably an extremely stupid question, but I wanted to
get
some verification. I’ve noticed that the minimum decimation rate you
can
use in all of the sample programs is 4 (giving you an effective sampling
rate of 16 MHz). If you are transmitting 1 real channel of data (16
bits)
at this rate, that seems to be maxing out the USB transfer rate of 32
MB/s.
Am I correct in my deduction that you need to use a decimation rate of
at
least 8 in order to transmit complex data (such as for FM demodulation)
successfully across the USB? Thanks.

Thanks,
John

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#2

Hi John -

16/D bits/sample x 64e10 samples/sec x 1 B/8 bits x 1 MB / 2^20 B <= 32
MB/sec

Therefore,

D >= 1664e10 /(328*2^20) = 3.814 -> 4

So, if you want to transmit twice as many sample across the bus…

D > = 21664e10 /(3282^20) = 7.63 -> 8

…you have to halve your sampling frequency.

Are you aware that there is a -8 option in some of the scripts that
allows you to send 8 bits instead of 16.

Hope that helps,

  • Lee

----- Original Message -----
From: jjw removed_email_address@domain.invalid
Date: Wednesday, April 5, 2006 5:31 pm
Subject: [Discuss-gnuradio] Bandwidth Across USB
To: removed_email_address@domain.invalid


#3

On Wed, Apr 05, 2006 at 02:30:30PM -0700, jjw wrote:

I know this is probably an extremely stupid question, but I wanted to get
some verification. I’ve noticed that the minimum decimation rate you can
use in all of the sample programs is 4 (giving you an effective sampling
rate of 16 MHz). If you are transmitting 1 real channel of data (16 bits)
at this rate,

Note that the standard FPGA build will not xfer a single real channel…

that seems to be maxing out the USB transfer rate of 32 MB/s.
Am I correct in my deduction that you need to use a decimation rate of at
least 8 in order to transmit complex data (such as for FM demodulation)
successfully across the USB? Thanks.

Yes, decim = 8 gives 64e6/8 = 8MS/s complex.

In general, you want to use the highest decimation factor that works
for your application. This offloads more of the crunching onto the
FPGA.

Eric


#4

John -

I must have been drunk when I wrote those equations. I wrote 64e10 when
I meant 64e6, and put the D in a weird place. Sorry for any confusion.
This makes more sense:

(16 bit/sample)(64e6/D sample/sec)(1/2^23 MB/bit) <= 32 MB/sec

therefore, for real

D >= 1664e6/(322^23) = 3.81 --> D = 4

and for complex

D >= 21664e6/(32*2^23) = 7.63 --> D = 8