B100 as clock master + B100 as clock slave

Hi everybody,

just a very quick question:

is it possible to enslave the clock of a B100 to the clock of another
B100
via the “REF IN” input or in some other way?
More precisely, is there a way to extract the clock signal from a B100
and
feed it into another B100 to enslave the latter to the former?

It would be great to be able to keep them in frequency and phase synch
that
way.

thank you

vince

On Fri, Mar 23, 2012 at 3:41 AM, Vincenzo P.
[email protected]wrote:

that way.

Vincenzo,

The ref in input on B100 is intended to accept a 10MHz signal. Multiple
B100s can be synchronized by using a common reference, but there is no
facility to lock two B100s to each other without a common external
reference.

–n

Hi Nick,
I have noticed that “j101” onboard the B100 outputs a 64 MHz reference.

Could it be possilble to feed that signal somehow into a second USRP
B100
to be used as a reference?

Could it be possible as an alternative to lock two B100 to an external
10
MHz reference while still working at 8Msps sample rate ?

my best regards

vincenzo

Il giorno 23 marzo 2012 16:54, Nick F. [email protected] ha scritto:

On Fri, Mar 23, 2012 at 10:18 AM, Vincenzo P.
[email protected]wrote:

Hi Nick,
I have noticed that “j101” onboard the B100 outputs a 64 MHz reference.

Could it be possilble to feed that signal somehow into a second USRP B100
to be used as a reference?

You would have to go through some gymnastics (read: soldering) to get
that
reference into the second B100, and some code rework to recalculate
clock
rates based on a 64MHz (or divisor of 64MHz) instead of 10MHz.

Could it be possible as an alternative to lock two B100 to an external 10
MHz reference while still working at 8Msps sample rate ?

Yes, this is what the ref in connectors are for. The external reference
is
independent of the sample rate. The B100s will continue to operate
normally, except locked to each other.

–n

On 03/23/2012 03:41 AM, Vincenzo P. wrote:

way.

It just dawned on me, and this may be a good idea in general:

There is a clock sync pin (cgen_sync_b in the fpga top level).
Presumably, a shared PPS could trigger the clock sync signal across
multiple B100. This would synchronously reset the phase across all N
devices. It would require a little FPGA work.

-Josh

Hi Nick, thanks for the answer.

Everything clear.
Just a further question.
Would a 0V-mean, 3.3V peak-to-peak sinusoid be correct as a reference
signal for the B100?

regards

vince

Il giorno 23 marzo 2012 18:30, Nick F. [email protected] ha scritto:

On 03/23/2012 01:56 PM, Josh B. wrote:

It just dawned on me, and this may be a good idea in general:

There is a clock sync pin (cgen_sync_b in the fpga top level).
Presumably, a shared PPS could trigger the clock sync signal across
multiple B100. This would synchronously reset the phase across all N
devices. It would require a little FPGA work.

-Josh

Would need to be a one-shot, yes?


Marcus L.
Principal Investigator
Shirleys Bay Radio Astronomy Consortium
http://www.sbrac.org

Josh,
I agree this would be a great feature.

vince

On Tue, Mar 27, 2012 at 7:26 AM, Vincenzo P.
[email protected]wrote:

Hi Nick, thanks for the answer.

Everything clear.
Just a further question.
Would a 0V-mean, 3.3V peak-to-peak sinusoid be correct as a reference
signal for the B100?

Use a 5-10dBm reference with no DC component. This corresponds to 1-2V
p-p.

–n

Hi Vince,

Changing a little the topic, have you managed to run your SoftDVB code
to
work on multiple USRPs in order to create a SFN DVB configuration?

Best regards,
Rafael D.

Thanks Nick,
that’s perfect.

Il giorno 27 marzo 2012 18:05, Nick F. [email protected] ha scritto:

Yes, there is a demo video on this from 2010 which you can view at my
youtube channel http://www.youtube.com/user/wwvince1
It’s called Soft-SFN.

regards

vince

Il giorno 27 marzo 2012 16:44, Rafael D. [email protected] ha
scritto:

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