I excuse myself on advance by my noob question…
I have an N210 with an SBX front end, and I want to experiment with
decoding signals at a lower resolution, rather than the default 12 bits
provided by the N210 ADCs. Does anyone know if (and how) can I limit the
resolution of the ADCs arbitrarily?
I am aware that I can reduce the resolution afterwards, mapping the
to a lower resolution in base band, but I’d really like to do that
the DDC at the FPGA.
Cheers to everyone!
Leonardo S. Cardoso